MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 55

• Manufacturer Part Number: MCIMX35WPDKJ
• Description: BOARD DEV FOR I.MX35
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r
• Type: MPUr

Specifications of MCIMX35WPDKJ

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: i.MX35
• Processor Series: i.MX35
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, JTAG
• Core: ARM11
• For Use With/related Products: i.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
ID
DQS (input)
DQ (input)
SDCLK
SDCLK
Figure 36. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 41
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value, and “low” is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 42
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 42. Mobile DDR SDRAM Read Cycle Timing Parameters
indicates SDRAM requirements. All output signals are driven by
indicates SDRAM requirements. All output signals are driven by
SD23
SD21
Data
Parameter
SD22
Data
NOTE
NOTE
Data
Data
Data
Data
tDQSCK
Symbol
tDQSQ
tQH
Data
Min. Max. Unit
2.3
—
—
Data
0.85
6.7
—
ns
ns
ns
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