MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 49
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1
Freescale Semiconductor
SD10 and SD11 are determined by SDRAM controller register settings.
SD10
SD11
SD7
ID
SDCLK
CAS
CKE
ADDR
RAS
WE
CS
Address hold time
Precharge cycle period
Auto precharge command period
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 35
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Don’t care
BA
Table 35. SDRAM Refresh Timing Parameters (continued)
indicates SDRAM requirements. All output signals are driven by
Figure 30. SDRAM Self-Refresh Cycle Timing Diagram
1
Parameter
SD16
1
NOTE
Symbol
tAH
tRP
tRC
SD16
Min.
1.8
1
2
Max.
20
—
4
clock
clock
Unit
ns
49
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