DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 35

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Introduction
CFI Flash Memory Map
© October 2009 Altera Corporation
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As you develop your own project using the Altera tools, you can program the flash
memory device so that your own design loads from flash memory into the FPGA on
power up. This appendix describes the preprogrammed contents of the common flash
interface (CFI) flash memory device on the Cyclone III LS FPGA development board
and the Nios II EDS tools involved with reprogramming the user portions of the flash
memory device.
The Cyclone III LS FPGA development board ships with the CFI flash device
preprogrammed with a default factory FPGA configuration for running the Board
Update Portal example design and a default user configuration for running the Board
Test System demonstration. There are several other factory software files written to
the CFI flash device to support the Board Update Portal. These software files were
created using the Nios II EDS, just as the hardware design was created using the
Quartus II software.
For more information about Altera development tools, refer to the
page on the Altera website.
Table A–1
PC48F4400P0VB00 CFI flash device. For the Board Update Portal to run correctly and
update designs in the user memory, this memory map must not be altered.
Table A–1. Byte Address Flash Memory Map
Unused
Unused
Unused
Unused
User software
Factory software
zipfs (html, web content)
Unused
User hardware 2
User hardware 1
Factory hardware
PFL option bits
Board information
Ethernet option bits
User design reset vector
Block Description
shows the default memory contents of the 512-Mbit (64-MByte) Intel
A. Programming the Flash Memory
24,320 KB
8,192 KB
8,192 KB
5,898 KB
6,422 KB
6,422 KB
6,422 KB
Size
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
0x02820000 - 0x03FDFFFF
0x02020000 - 0x0281FFFF
0x01820000 - 0x0201FFFF
0x01280000 - 0x0181FFFF
0x00C60000 - 0x0127FFFF
0x00640000 - 0x00C5FFFF
0x00020000 - 0x0063FFFF
0x00018000 - 0x0001FFFF
0x00010000 - 0x00017FFF
0x00008000 - 0x0000FFFF
0x00000000 - 0x00007FFF
0x03FE8000 - 0x03FEFFFF
0x03FE0000 - 0x03FE7FFF
0x03FF8000 - 0x03FFFFFF
0x03FF0000 - 0x03FF7FFF
Cyclone III LS FPGA Development Kit User Guide
Address Range
Design Software
Device