DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 23

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 6: Board Test System
Using the Board Test System
© October 2009 Altera Corporation
1
Table 6–1. MAX II Registers

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Because the Config tab requires that a specific design is running in the FPGA, writing
a 0 to SRST or changing the PSO value can cause the Board Test System to stop
running.
System Reset
(SRST)
Page Select Register
(PSR)
Page Select Override
(PSO)
Page Select Switch
(PSS)
Oscillator Control
Register 1 (OCR1)
Register Name
PSO—Sets the MAX II PSO register. The following options are available:


PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to
for more information.
PSS—Displays the MAX II PSS register value. Refer to
available options.
OCR1—Sets the MAX II OCR1 register. Refer to
options.
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to
Use PSR—Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
Use PSS—Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
Write only
Read / Write
Read / Write
Read only
Read / Write
Read/Write
Capability
Set to 0 to initiate an FPGA reconfiguration.
Determines which of the two pages of flash memory to use
for FPGA reconfiguration. The flash memory ships with
pages 0 and 1 preconfigured.
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Holds the current value of the illuminated PROGRAM LED
(D29-D31) based on the following encoding:


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Determines the U17 oscillator output frequency based on
the following options:

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0 = PROGRAM LED0 LED (D31) and corresponds to the
flash memory page for the factory hardware design
1 = PROGRAM LED1 LED (D30) and corresponds to the
flash memory page for the user hardware 1 design
2 = PROGRAM LED2 LED (D29) and corresponds to the
flash memory page for the user hardware 2 design
0 = 100 MHz
1 = 125 MHz
2 = 150 MHz
3 = 156.25 MHz
Cyclone III LS FPGA Development Kit User Guide
Table 6–1
Table 6–1
Description
Table 6–1
for the list of available
for more information.
for the list of
Table 6–1
6–5