DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 98

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–98
Table 1–62. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 7)
Stratix III Device Handbook, Volume 2
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
4mA
8mA
12mA
16mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
Table 1–63
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
Industrial
t
t
t
t
t
t
t
t
-0.754
-0.835
-0.754
-0.835
-0.916
-0.735
-0.916
-0.735
0.871
1.087
0.871
1.087
1.031
0.986
1.031
0.986
co
co
co
co
co
co
co
co
Industrial
Fast Model
lists the EP3SL110 column pins output timing parameters for single-ended
3.439
3.829
3.372
3.762
3.286
3.676
3.279
3.669
Fast Model
Commercial
-0.795
-0.832
-0.795
-0.832
-0.894
-0.735
-0.894
-0.735
0.928
1.100
0.928
1.100
1.026
1.002
1.026
1.002
Commercial
3.439
3.829
3.372
3.762
3.286
3.676
3.279
3.669
-1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639
-1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619
-1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639
-1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
1.324
1.765
1.324
1.765
1.437
1.649
1.437
1.649
1.1 V
V
C2
CCL
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
4.768 5.145 5.638 5.507 5.801 5.145 5.638 5.507 5.801
5.344 5.778 6.326 6.168 6.550 5.778 6.326 6.168 6.550
4.659 5.034 5.525 5.394 5.688 5.034 5.525 5.394 5.688
5.235 5.667 6.213 6.055 6.437 5.667 6.213 6.055 6.437
4.556 4.936 5.433 5.302 5.596 4.936 5.433 5.302 5.596
5.131 5.568 6.121 5.963 6.345 5.568 6.121 5.963 6.345
4.539 4.908 5.392 5.261 5.555 4.908 5.392 5.261 5.555
5.114 5.540 6.080 5.922 6.304 5.540 6.080 5.922 6.304
1.1 V
V
C2
CCL
=
1.432
1.995
1.432
1.995
1.649
1.861
1.649
1.861
1.1 V
V
C3
CCL
=
1.1 V
V
C3
CCL
=
1.542
2.226
1.542
2.226
1.795
1.973
1.795
1.973
1.1 V
V
C4
CCL
1.1 V
=
V
C4
CCL
=
1.485
2.111
1.485
2.111
1.825
1.857
1.825
1.857
1.1 V
V
CCL
1.1 V
V
=
CCL
C4L
=
C4L
1.815
2.053
1.815
2.053
2.069
1.801
2.069
1.801
0.9 V
V
CCL
0.9 V
V
CCL
=
© July 2010 Altera Corporation
=
1.443
2.008
1.443
2.008
1.681
1.871
1.681
1.871
1.1 V
V
1.1 V
I3
CCL
V
I3
CCL
=
=
1.550
2.242
1.550
2.242
1.799
1.993
1.799
1.993
1.1 V
V
1.1 V
V
I4
CCL
I4
CCL
=
=
I/O Timing
1.496
2.125
1.496
2.125
1.836
1.875
1.836
1.875
1.1 V
1.1 V
V
V
CCL
CCL
=
=
I4L
I4L
0.9 V
1.858
2.100
1.858
2.100
2.109
1.851
2.109
1.851
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns