DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 327

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Glossary
Table 1.
© July 2010 Altera Corporation
Glossary Table (Part 2 of 4)
Letter
M
K
L
N
O
P
Q
R
J
Specifications
Specifications
JTAG Timing
Subject
PLL
—
—
—
—
—
—
R
J
L
High-Speed I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications are in the following figure:
The block diagram shown in the following figure highlights the PLL Specification parameters:
Diagram of PLL Specifications (1)
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to Stratix III device).
TMS
TDI
TDO
TCK
Core Clock
Key
CLK
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
f
INPFD
Definitions
t
JPCO
PFD
—
—
—
—
—
—
M
t
JPSU
CP
LF
VCO
t
JPH
f
Stratix III Device Handbook, Volume 2
VCO
Counters
C0..C9
t
JPXZ
CLKOUT Pins
f
f
OUT_EXT
OUT
GCLK
RCLK
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