DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 316

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–316
Table 1–164. EP3SL150 Column Pin Periphery Clock Timing Specifications
Table 1–165. EP3SL150 Row Pin Periphery Clock Timing Specifications
Table 1–166. EP3SL200 Column Pin Global Clock Timing Specifications
Table 1–167. EP3SL200 Row Pin Global Clock Timing Specifications
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.040
-0.040
-0.080
1.537
1.537
1.438
1.356
0.002
2.237
2.237
0.032
0.032
2.208
2.126
0.102
0.020
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–164
devices.
EP3SL200 Clock Timing Parameters
Table 1–166
devices.
Commercial
Commercial
Commercial
Commercial
-0.012
-0.012
-0.015
1.550
1.550
1.505
1.414
0.076
2.264
2.264
0.060
0.060
2.371
2.280
0.174
0.083
and
and
Table 1–165
Table 1–167
-0.235 -0.326 -0.267
-0.235 -0.326 -0.267
-0.183 -0.266 -0.217
-0.328 -0.429 -0.398
-0.177 -0.219 -0.137
-0.177 -0.219 -0.137
-0.085 -0.115 -0.076
-0.237 -0.278 -0.257
2.268
2.268
2.159
2.014
3.331
3.331
3.453
3.301
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.535
2.535
2.429
2.266
3.416
3.416
3.526
3.366
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the periphery clock timing parameters for EP3SL150
list the global clock timing parameters for EP3SL200
=
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
2.929
2.929
2.783
2.602
3.842
3.842
3.900
3.719
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.234
-0.234
-0.185
-0.356
-0.122
-0.122
-0.043
-0.214
2.812
2.812
2.657
2.486
3.686
3.686
3.747
3.576
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.206
-0.365
-0.063
-0.222
3.354
3.354
0.002
0.002
2.934
2.775
4.345
4.345
4.190
4.031
0.088
0.088
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.326
-0.326
-0.220
-0.390
-0.219
-0.219
-0.067
-0.237
2.535
2.535
2.475
2.305
3.416
3.416
3.601
3.433
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
=
=
=
=
© July 2010 Altera Corporation
-0.267
-0.267
-0.182
-0.371
2.929
2.929
2.838
2.649
3.834
3.834
0.287
0.287
3.977
3.788
0.409
0.220
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.234
-0.234
-0.132 -0.260
-0.311 -0.419
-0.122
-0.122
-0.043 -0.063
-0.214 -0.222
2.812
2.812
2.725
2.546
3.686
3.686
3.747
3.576
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
I/O Timing
3.354
3.354
0.002
0.002
2.972
2.813
4.345
4.345
0.088
0.088
4.190
4.031
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns