DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 267

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–123. EP3SE110 Column Pins Output Timing Parameters (Part 7 of 7)
Table 1–124. EP3SE110 Row Pins Output Timing Parameters (Part 1 of 5)
© July 2010 Altera Corporation
1.2-V
HSTL
CLASS I
1.2-V
HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
Standard
Standard
I/O
I/O
4mA
6mA
8mA
10mA
12mA
16mA
—
—
4mA
8mA
12mA
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–124
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
Industrial Commercial
Industrial
3.336
3.716
3.328
3.707
3.329
3.707
3.318
3.697
3.318
3.697
3.339
3.718
3.442
3.821
3.442
3.821
3.208
1.452
3.142
1.359
3.063
1.260
lists the EP3SE110 row pins output timing parameters for single-ended
Fast Model
Fast Model
Commercial
3.336
3.728
3.328
3.720
3.329
3.721
3.318
3.710
3.318
3.710
3.339
3.731
3.442
3.834
3.442
3.834
3.456
1.625
3.385
1.554
3.296
1.465
4.703
5.289
4.694
5.280
4.702
5.287
4.689
5.274
4.689
5.274
4.705
5.290
4.750
5.335
4.750
5.335
1.1 V
V
C2
CCL
4.797 5.180 5.703 5.543 5.850 5.304 5.827 5.696 5.930
2.008 2.086 2.326 2.346 2.347 2.239 2.435 2.455 2.342
4.687 5.069 5.589 5.429 5.736 5.191 5.712 5.581 5.815
1.898 1.975 2.181 2.201 2.202 2.098 2.286 2.306 2.193
4.581 4.969 5.493 5.333 5.640 5.092 5.612 5.481 5.715
1.792 1.875 2.053 2.073 2.074 1.971 2.154 2.174 2.061
1.1 V
V
C2
=
CCL
=
5.096
5.719
5.087
5.710
5.095
5.718
5.082
5.704
5.082
5.705
5.097
5.720
5.131
5.756
5.131
5.756
1.1 V
V
C3
1.1 V
CCL
V
C3
CCL
=
=
5.577
6.333
5.568
6.324
5.577
6.333
5.563
6.319
5.564
6.320
5.577
6.333
5.602
6.358
5.602
6.358
1.1 V
V
1.1 V
V
C4
CCL
C4
CCL
=
=
5.442
6.169
5.433
6.160
5.442
6.169
5.428
6.155
5.429
6.156
5.442
6.169
5.467
6.194
5.467
6.194
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
5.754
6.571
5.745
6.562
5.754
6.571
5.740
6.557
5.741
6.558
5.754
6.571
5.779
6.596
5.779
6.596
Stratix III Device Handbook, Volume 2
0.9 V
0.9 V
V
V
CCL
CCL
=
=
1.1 V
V
5.096
5.719
5.087
5.710
5.095
5.718
5.082
5.704
5.082
5.705
5.097
5.720
5.131
5.756
5.131
5.756
1.1 V
V
I3
CCL
CCL
I3
=
=
1.1 V
V
5.577
6.333
5.568
6.324
5.577
6.333
5.563
6.319
5.564
6.320
5.577
6.333
5.602
6.358
5.602
6.358
1.1 V
CCL
V
I4
CCL
I4
=
=
1.1 V
V
5.442
6.169
5.433
6.160
5.442
6.169
5.428
6.155
5.429
6.156
5.442
6.169
5.467
6.194
5.467
6.194
CCL
1.1 V
V
1–267
CCL
=
I4L
=
I4L
0.9 V
V
CCL
5.754
6.571
5.745
6.562
5.754
6.571
5.740
6.557
5.741
6.558
5.754
6.571
5.779
6.596
5.779
6.596
0.9 V
V
=
CCL
=
Units
ns
ns
ns
ns
ns
ns
UnitS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns