DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 112

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–112
Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 4)
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
1.5-V
SSTL CLASS II
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS II
DIFFERENTIAL
2.5-V
SSTL CLASS I
DIFFERENTIAL
2.5-V
SSTL CLASS II
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
I/O Standard
I/O Standard
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
—
—
—
—
Table 1–67
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
Industrial Commercial
-0.733
-0.891
-0.747
-0.877
-0.747
-0.877
-0.756
-0.868
-0.756
-0.868
0.850
1.145
0.864
1.131
0.864
1.131
0.873
1.122
0.873
1.122
Fast Model
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
lists the EP3SL110 column pins output timing parameters for differential
Industrial
3.100
1.308
3.096
1.304
3.100
1.308
3.096
1.304
-0.777
-0.890
-0.789
-0.878
-0.789
-0.878
-0.798
-0.869
-0.798
-0.869
0.910
1.160
0.922
1.148
0.922
1.148
0.931
1.139
0.931
1.139
Fast Model
Commercial
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623
1.311
1.853
1.321
1.840
1.321
1.840
1.336
1.825
1.336
1.825
3.330
1.480
3.333
1.483
3.330
1.480
3.333
1.483
1.1 V
V
C2
CCL
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1.430
2.090
1.440
2.080
1.440
2.080
1.454
2.064
1.454
2.064
1.1 V
V
C3
CCL
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
1.1 V
V
C2
CCL
=
=
1.551
2.322
1.569
2.304
1.569
2.304
1.579
2.293
1.579
2.293
1.1 V
V
1.1 V
V
C4
CCL
C3
CCL
=
=
1.490
2.203
1.508
2.185
1.508
2.185
1.518
2.173
1.518
2.173
1.1 V
1.1 V
V
V
C4
CCL
CCL
=
=
C4L
1.1 V
V
1.818
2.139
1.836
2.121
1.836
2.121
1.847
2.110
1.847
2.110
0.9 V
V
CCL
CCL
=
C4L
=
© July 2010 Altera Corporation
0.9 V
V
CCL
1.438
2.108
1.449
2.097
1.449
2.097
1.459
2.086
1.459
2.086
1.1 V
V
=
I3
CCL
=
1.1 V
V
CCL
I3
-1.319
-1.831
-1.336
-1.814
-1.336
-1.814
-1.337
-1.805
-1.337
-1.805
1.559
2.344
1.576
2.327
1.576
2.327
1.582
2.321
1.582
2.321
=
1.1 V
V
I4
CCL
=
1.1 V
V
I4
CCL
I/O Timing
=
-1.271
-1.737
-1.288
-1.720
-1.288
-1.720
-1.291
-1.711
-1.291
-1.711
1.499
2.222
1.516
2.205
1.516
2.205
1.521
2.197
1.521
2.197
1.1 V
V
CCL
1.1 V
V
=
CCL
I4L
=
I4L
-1.642
-1.702
-1.659
-1.685
-1.659
-1.685
-1.661
-1.674
-1.661
-1.674
1.862
2.187
1.879
2.170
1.879
2.170
1.886
2.163
1.886
2.163
0.9 V
V
CCL
0.9 V
V
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns