DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 322

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–322
Table 1–188. EP3SE80 Column Pin Periphery Clock Timing Specifications
Table 1–189. EP3SE80 Row Pin Periphery Clock Timing Specifications
Table 1–190. EP3SE110 Column Pin Global Clock Timing Specifications
Table 1–191. EP3SE110 Row Pin Global Clock Timing Specifications
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.028
-0.028
-0.078
-0.020
-0.020
-0.070
1.564
1.564
1.441
1.359
0.004
2.046
2.046
1.985
1.903
0.012
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–188
devices.
EP3SE110 Clock Timing Parameters
Table 1–190
devices.
Commercial
Commercial
Commercial
Commercial
-0.006
-0.006
-0.014
-0.034
-0.034
-0.007
1.585
1.584
1.503
1.412
0.077
2.046
2.046
2.130
2.039
0.084
and
and
Table 1–189
Table 1–191
-0.234 -0.327 -0.270
-0.234 -0.327 -0.270
-0.186 -0.268 -0.243
-0.328 -0.431 -0.424
-0.265 -0.311 -0.267
-0.265 -0.311 -0.267
-0.180 -0.253 -0.223
-0.322 -0.416 -0.404
2.309
2.308
2.156
2.011
2.868
2.868
2.928
2.786
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.566
2.566
2.429
2.266
3.144
3.144
3.183
3.020
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the periphery clock timing parameters for EP3SE80
list the global clock timing parameters for EP3SE110
=
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
2.962
2.962
2.776
2.595
3.524
3.524
3.546
3.365
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.193
-0.193
-0.177
-0.348
-0.198
-0.198
-0.173
-0.344
2.838
2.844
2.665
2.494
3.429
3.429
3.437
3.266
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.018
-0.018
-0.238
-0.397
-0.034
-0.034
-0.223
-0.382
3.377
3.377
2.934
2.775
3.989
3.989
3.772
3.613
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.327
-0.327
-0.219
-0.389
-0.311
-0.311
-0.207
-0.377
2.566
2.566
2.477
2.307
3.144
3.144
3.250
3.082
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
=
=
=
=
© July 2010 Altera Corporation
-0.270
-0.270
-0.177
-0.366
-0.267
-0.267
-0.173
-0.362
2.962
2.962
2.828
2.639
3.524
3.524
3.615
3.426
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.193 -0.018
-0.193 -0.018
-0.128 -0.287
-0.307 -0.446
-0.198 -0.034
-0.198 -0.034
-0.123 -0.267
-0.302 -0.426
2.838
2.844
2.711
2.532
3.429
3.429
3.507
3.328
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
I/O Timing
3.377
3.377
2.959
2.800
3.989
3.989
3.815
3.656
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns