DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 26

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–26
Table 1–28. Sampling Window (SW)—Read Side
Stratix III Device Handbook, Volume 2
DDR3 SDRAM (with 8 or
10 tap phase offset,
300 MHz–400 MHz)
DDR3 SDRAM (with
Deskew circuitry,
401 MHz–533 MHz)
DDR3 SDRAM
(Non-leveling interface)
DDR2 SDRAM Differential
DQS
DDR2 SDRAM
Single-ended DQS
DDR SDRAM
Single-ended DQS
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation
RLDRAM II
RLDRAM II
Notes to
(1) The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups
(2) For implementation, refer to the “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” section in the
wrapping over Column I/Os and Row I/Os of the device.
Interfaces in Stratix III Devices
Memory Type
Table
(2)
(2)
1–28:
.
Standard
chapter.
1.5-V
1.5-V
1.5-V
1.8-V
1.8-V
2.5-V
1.5-V
HSTL
1.5-V
HSTL
1.8-V
HSTL
1.8-V
HSTL
1.5-V
HSTL
1.8-V
HSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
I/O
×9, ×18,
×9, ×18,
×9, ×18
×9, ×18
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
Width
×36
×36
×36
×36
(Note 1)
Setup
172
300
172
181
231
231
261
261
261
261
211
211
V
CCL
SW (ps)
= 1.1 V
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
C2
Hold
296
213
296
306
256
256
286
328
286
328
336
336
Setup
234
234
234
284
284
314
314
314
314
264
264
V
—
CCL
SW (ps)
C3, I3
= 1.1 V
Hold
296
296
326
276
261
291
337
291
337
356
356
—
Setup
257
257
257
307
307
337
337
337
337
287
287
V
—
CCL
SW (ps)
C4, I4
= 1.1 V
© July 2010 Altera Corporation
Hold
311
311
326
276
261
291
350
291
350
356
356
—
Switching Characteristics
Setup
257
257
257
307
307
337
337
337
337
287
287
V
—
C4L, I4L
CCL
SW (ps)
= 1.1 V
Hold
311
311
326
276
261
291
350
291
350
356
356
—
External Memory
Setup
257
257
257
307
307
337
337
337
337
287
287
V
—
CCL
C4L, I4L
SW (ps)
= 0.9 V
Hold
311
311
326
276
261
291
350
291
350
356
356
—