STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 98
STEVAL-IFS012V1
Manufacturer Part Number
STEVAL-IFS012V1
Description
BOARD ST72651AR6/STTS75/STLM20
Manufacturer
STMicroelectronics
Specifications of STEVAL-IFS012V1
Sensor Type
Temperature
Sensing Range
Depends on IC
Interface
I²C, USB
Sensitivity
Depends on IC
Voltage - Supply
5V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651AR6, STTS75, STLM20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8419
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ST72651AR6
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 59. Data Clock Timing Diagram
98/161
(from slave)
(from slave)
59).
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
SS
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
Doc ID 7215 Rev 4
CPHA =0
CPHA =1
Bit 4
Bit 4
Bit 4
Bit 4
Figure
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit3
Bit3
Bit3
Bit3
59, shows an SPI transfer with the four
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSBit
LSBit
LSBit
LSBit
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