STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 72

• Manufacturer Part Number: STEVAL-IFS012V1
• Description: BOARD ST72651AR6/STTS75/STLM20
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS012V1

• Sensor Type: Temperature
• Sensing Range: Depends on IC
• Interface: I²C, USB
• Sensitivity: Depends on IC
• Voltage - Supply: 5V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651AR6, STTS75, STLM20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8419

ST72651AR6
USB INTERFACE (Cont’d)
ENDPOINT
(EP1TXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 1
transmission. Bits 2:0 are also reset by a USB re-
set, either received from the USB or forced
through the FRES bit in the CTLR register.
Bit 3 = CTR_TX Correct Transmission Transfer.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1
1: Correct transfer in transmission on Endpoint 1
Bit 2 = DTOG_TX Data Toggle, for transmission
transfers.
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by hardware, at the receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
Bits 1:0 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, which is listed below
Table 23. Transmission Status Encoding
72/161
1
STAT_TX1 STAT_TX0
7
0
0
0
1
1
0
1
0
0
1
0
1
TRANSMISSION
0
DISABLED: transmission
transfers cannot be executed.
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
VALID: this endpoint is ena-
bled for transmission.
CTR_T
X
DTOG
Meaning
_TX
STAT_
REGISTER
TX1
Doc ID 7215 Rev 4
STAT_
TX0
0
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
ENDPOINT
(EP2RXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling endpoint 2 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the CTLR register.
Bits 7:6 = MOD[1:0] Endpoint 2 mode.
These bits are set and cleared by software. They
select the Endpoint 2 mode (See
Figure
Notes:
1. Before selecting Download mode, software
must write the maximum packet size value (for in-
stance 64) in the CNT2RXR register and write the
STAT_RX bits in the EP2RXR register to VALID.
2. Before selecting Upload mode, software must
write the maximum packet size value (for instance
64) in the CNT2TXR register and write the
STAT_TX bits in the EP2TXR register to NAK.
MOD1 MOD0
MOD1 MOD0
7
0
0
1
39).
0
1
0
Normal mode: Endpoint 2 is managed by
user software
Upload mode to USB data buffer: Bulk
mode IN under hardware control from
DTC
Download mode from USB data buffer:
Bulk mode OUT under hardware control
to DTC
0
2
1
2
RECEPTION
.
0
CTR_R
X
Mode
DTOG
_RX
Figure 38
STAT_
REGISTER
RX1
STAT_
RX0
and
0