STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 80

• Manufacturer Part Number: STEVAL-IFS006V1
• Description: BOARD EVAL 8BIT MICRO + TDE1708
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS006V1

• Design Resources: STEVAL-IFS006V1 Bill of Material
• Sensor Type: Proximity
• Interface: I²C
• Voltage - Supply: 6 V ~ 48 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST7FLITEUS5, TDE1708
• Processor To Be Evaluated: ST7LITEUS5
• Data Bus Width: 8 bit
• Operating Supply Voltage: 6 V to 48 V
• Silicon Manufacturer: ST Micro
• Silicon Core Number: TDE1708DFT
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Proximity Switch
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6403; STEVAL-IFS006V1

On-chip peripherals
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Figure 36. ADC block diagram
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
R
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
A/D conversion phases
The A/D conversion is based on two conversion phases:
●
●
AIN
AIN0
AIN1
AINx
Sample capacitor loading [duration: t
During this phase, the V
sample capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is computed (8 successive approximations
is the maximum recommended impedance for an analog input signal. If the impedance
f
CPU
ANALOG
DIV 2
MUX
EOC SPEED ADON
AIN
AIN
3
ADCDRH
) is greater than V
) is lower than V
0
1
AIN
HOLD
DIV 4
input voltage to be measured is loaded into the C
0
R
ADCDRL
ADC
D9
]
0
CH2
D8
SSA
SAMPLE
SLOW
DDA
bit
1
0
CH1
D7
HOLD CONTROL
(low-level voltage reference) then the
(high-level voltage reference) then the
0
CH0
D6
]
0
f
C
ADC
ADC
D5
ADCCSR
0
D4
0
ANALOG TO DIGITAL
D3
SLOW
CONVERTER
ST7LITEUS2, ST7LITEUS5
D2
0
D1
D0
ADC