SOUNDBITE Freescale Semiconductor, SOUNDBITE Datasheet - Page 6

• Manufacturer Part Number: SOUNDBITE
• Description: BOARD DEMO AUDIO DEVELOPMENT
• Manufacturer: Freescale Semiconductor
• Series: Symphony™ soundBiter

Specifications of SOUNDBITE

• Main Purpose: Audio, Audio Processing
• Utilized Ic / Part: DSPB56371
• Primary Attributes: Up to 8 channels of digital audio
• Secondary Attributes: USB, I2C, SPI Interface
• Processor To Be Evaluated: DSP56371
• Data Bus Width: 24 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DSP56371 Overview
2.4.2
The AGU performs the effective address calculations using integer arithmetic necessary to address data
operands in memory and contains the registers used to generate the addresses. It implements four types of
arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry. The AGU operates in parallel
with other chip resources to minimize address-generation overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of
register triplets, and each register triplet is composed of an address register, an offset register and a
modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset
adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo
value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is
also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference
between them is that the carry propagates in opposite directions. Test logic determines which of the three
summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register file during one
instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used
in the address register update calculation. The modifier value is decoded in the Address ALU.
2.4.3
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception
processing. The PCU implements a seven-stage pipeline and controls the different processing states of the
DSP56300 core. The PCU consists of the following three hardware blocks:
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary
for pipeline control. The PAG contains all the hardware needed for program address generation, system
stack and loop control. The Program interrupt controller arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD and NMI) and generates the
appropriate interrupt vector address.
PCU features include the following:
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Program decode controller (PDC)
Program address generator (PAG)
Program interrupt controller
Position independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Address Generation Unit (AGU)
Program Control Unit (PCU)
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor