SOUNDBITE Freescale Semiconductor, SOUNDBITE Datasheet - Page 50

• Manufacturer Part Number: SOUNDBITE
• Description: BOARD DEMO AUDIO DEVELOPMENT
• Manufacturer: Freescale Semiconductor
• Series: Symphony™ soundBiter

Specifications of SOUNDBITE

• Main Purpose: Audio, Audio Processing
• Utilized Ic / Part: DSPB56371
• Primary Attributes: Up to 8 channels of digital audio
• Secondary Attributes: USB, I2C, SPI Interface
• Processor To Be Evaluated: DSP56371
• Data Bus Width: 24 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Serial Audio Interface Timing
50
Note:
No.
88 SCKT edge to transmitter #0 drive enable
89 FST input (bl, wr) setup time before SCKT
90 FST input (wl) setup time before SCKT edge
91 FST input hold time after SCKT edge
92 FST input (wl) to data out enable from high
93 FST input (wl) to transmitter #0 drive enable
94 Flag output valid after SCKT edge
95 HCKR/HCKT clock cycle
96 HCKT input edge to SCKT output
97 HCKR input edge to SCKR output
deassertion
edge
impedance
assertion
1. V
2. SCKT(SCKT pin) = transmit clock
3. bl = bit length
4. i ck = internal clock
5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
7. Periodically sampled and not 100% tested
8. ESAI_1 specs match those of ESAI_0
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
wl = word length
wr = word length relative
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
CORE_VDD
6
7
Characteristics
= 1.25 ± 0.05 V; T
Table 22. Enhanced Serial Audio Interface Timing (continued)
1, 2, 3
J
= –40°C to 115°C for 150 MHz; T
DSP56371 Data Sheet, Rev. 4.1
Symbol
—
—
—
—
—
—
—
—
—
—
J
= 0°C to 100°C for 181 MHz; C
Expression
2 x T
—
—
—
—
—
—
—
—
—
C
21.0
21.0
13.4
Min
2.0
2.0
4.0
0.0
—
—
—
—
—
—
—
—
L
= 50 pF
Max
34.0
20.0
27.0
31.0
32.0
18.0
18.0
18.0
—
—
—
—
—
—
—
Freescale Semiconductor
Condition
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
—
—
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns