SI5356-EVB Silicon Laboratories Inc, SI5356-EVB Datasheet

EVALUATION BOARD FOR SI5356

SI5356-EVB

Manufacturer Part Number
SI5356-EVB
Description
EVALUATION BOARD FOR SI5356
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5356-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5356
Technology Type
Evaluation Board
For Use With/related Products
Si5356
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1750
I
Q
Features
Applications
Description
The Si5356 is a highly flexible, I
synthesizing four completely non-integer related frequencies up to 200 MHz. The
device has four banks of outputs with each bank supporting two CMOS outputs at
the same frequency. Using Silicon Laboratories' patented MultiSynth fractional
divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis
error regardless of configuration, enabling the replacement of multiple clock ICs
and crystal oscillators with a single device. Each output bank is independently
configurable to support 1.8, 2.5, or 3.3 V. The device is programmable via an I
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply.
Functional Block Diagram
Preliminary Rev. 0.3 2/11
2
Generates any frequency from 1 to
200 MHz on each of the 4 output banks
Programmable frequency configuration
Guaranteed 0 ppm frequency synthesis
error for any combination of frequencies
25 or 27 MHz xtal or 5–200 MHz input clk
Eight CMOS clock outputs
Easy to use programming software
Configurable “triple A” spread spectrum:
any clock, any frequency, and with any
spread amount
Programmable output phase adjustment
with <20 ps error
Interrupt pin indicates LOS or LOL
Printers
Audio/video
DSLAM
C P
UAD
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
ROGRAMMABLE
F
R E Q U E N C Y
2
C programmable clock generator capable of
Copyright © 2011 by Silicon Laboratories
8-O
Storage area networks
Switches/routers
Servers
, A
OEB pin disables all outputs or per
bank OEB control via I
Low jitter: 50 ps pk-pk (typ), 100 ps
pk-pk period jitter (max)
Excellent PSRR performance
eliminates need for external power
supply filtering
Low power: 45 mA
Core VDD: 1.8, 2.5, or 3.3 V
Separate VDDO for each bank of
outputs: 1.8, 2.5, or 3.3 V
Small size: 4x4 mm 24-QFN
Industrial temperature range:
–40 to +85 °C
UTPUT
NY
- F
R E Q U E N C Y
C
LOCK
2
C
2
C/
G
CLKIN
SSC_DIS
I2C_LSB
E NE RAT OR
1 – 2 0 0 M H
CLKIN
XA
XB
P1
P4
P5
OEB
XA
XB
1
2
3
4
5
6
Ordering Information:
1
2
3
4
5
6
7
24
Pin Assignments
7
24
See page 24.
23
8
8
23
Top View
Si5356
Top View
9
22
GND
9
22
GND
GND
GND
10
21
10
21
11
20
11
20
Z
12
19
12
19
,
18
17
16
15
14
13
18
17
16
15
14
13
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOB
Si5356
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOB

Related parts for SI5356-EVB

SI5356-EVB Summary of contents

Page 1

... DSLAM  Description 2 The Si5356 is a highly flexible programmable clock generator capable of synthesizing four completely non-integer related frequencies up to 200 MHz. The device has four banks of outputs with each bank supporting two CMOS outputs at the same frequency. Using Silicon Laboratories' patented MultiSynth fractional ...

Page 2

... Si5356 2 Preliminary Rev. 0.3 ...

Page 3

... Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5. Configuring the Si5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 ...

Page 4

... Si5356 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10 Parameter Ambient Temperature Core Supply Voltage Output Buffer Supply Voltage Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted ...

Page 5

... CLKIN, I2C_LSB IH SSC_DIS, OEB V CLKIN, I2C_LSB IL SSC_DIS, OEB V Pins: CLK0– – Pins: CLK0– Pin: LOS OLINTR Preliminary Rev. 0.3 Si5356 Min Typ Max Units — 0 — 3.63 DD 0.85 — 1.3 –0.2 — 0 — — 0.3 V – 0.3 — — DDO — ...

Page 6

... Si5356 Table 4. AC Characteristics (V = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10 Parameter Input Clock Clock Input Frequency Clock Input Rise/Fall Time Clock Input Duty Cycle Clock Input Capacitance Output Clocks Clock Output Frequency Clock Output Frequency Synthesis Resolution Output Load Capacitance Clock Output Rise/Fall Time ...

Page 7

... Standard Mode Min Max –0.5 0.3*V 0.7*V 3.63 DDI2C N/A N 2 1.8 V N/A N/A –10 10 — 4 DDI2C 25 35 Preliminary Rev. 0.3 Si5356 Min Typ Max Units — 25 — MHz — 27 — MHz — — 4 — — 100 — — 75 100 — ...

Page 8

... PAD Ethernet PHY 125 MHz XB 22 CLK0 CLKIN 21 x CLK1 48 MHz 18 CLK2 17 x CLK3 14 INTR CLK4 Si5356 13 SDA x CLK5 SCL 10 CLK6 I2C_LSB 9 x CLK7 35.788 MHz SSC_DIS Touchscreen OEB PAD 23 23 PAD Preliminary Rev. 0.3 Ethernet Ethernet PHY Ethernet PHY Ethernet ...

Page 9

... Programming... menu option. An NVM file can be used by factory to prepare custom pre-programmed devices. 3.2. Input Configuration The Si5356 input can be driven from either an external crystal or a reference clock. If the crystal input option is used, the Si5356 operates as a free-running clock generator. In this mode of operation the device requires a low cost MHz fundamental mode crystal connected across XA and XB as shown in Figure 1 ...

Page 10

... Si5356 Si5356 XA XTAL XB Figure 1. Connecting an XTAL to the Si5356 For synchronous timing applications, the Si5356 can lock 200 MHz CMOS reference clock. A typical interface circuit is shown in Figure 2. A series termination resistor matching the driver’s output impedance to the impedance of the transmission line is recommended to reduce reflections ...

Page 11

... Si5356A-Axxxxx-GM). 3.5.1. Ordering a Custom NVM Configuration The Si5356 is orderable with a factory-programmed custom NVM configuration. This is the simplest way of using the Si5356 since it generates the desired output is the frequencies at power-up or after a power-on reset OUT (POR). This default configuration can be reconfigured in RAM through the I “ ...

Page 12

... An alternative to ordering an Si5356 with a custom NVM configuration is to use the field programming kit (Si5338/56-PROG-EVB) to write directly to the NVM of a "blank" Si5356. Since NVM is an OTP memory, it can only be written once. The default configuration can be reconfigured by writing to RAM through the I (see “3.5.2. Creating a New Configuration for RAM”). ...

Page 13

... CMOS Output Drivers The Si5356 has 4 banks of outputs with each bank comprised of 2 clocks for a total of 8 CMOS outputs per device. By default, each bank of CMOS output clocks are in-phase. Alternatively, each output clock can be inverted. This feature enables each output pair to operate as a differential CMOS clock ...

Page 14

... I standard. To accommodate multiple Si5356 devices on 2 the same I C bus, the Si5356 has pin 3 as I2C_LSB. The complete 7-bit I2C bus address for the device is 70h or 71h depending upon the state of the I2C_LSB pin. In binary, this is written as 111 000[I2C_LSB]. See ...

Page 15

... The programming of Spread Spectrum is made easy by using the Si5356 Programmer. Spread spectrum on all the outputs can be enabled or disabled using the SSC_DIS pin, or independently for each output bank 2 through the I C interface. ...

Page 16

... Power Supply Considerations The Si5356 has two core supply voltage pins ( enabling the device to be used in mixed supply applications. The Si5356 does not require ferrite beads for DDOD power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter ...

Page 17

... ClockBuilder, refer to “AN565: Configuring the Si5356A” for a detailed description of the Si5356 registers and their usage. Also refer to “AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products” for a working application example of register programming using the Silicon Labs' C8051F301 MCU ...

Page 18

... XA and XB input clock is used, this pin should be tied to GND. 3 I2C_LSB LSB Address Bit This pin is the least significant bit of the Si5356 I devices to occupy the same I 4 CLKIN I Single-Ended Input Clock single-ended clock is used as the device frequency reference, connect it to this pin. ...

Page 19

... Table 8. Si5356 Pin Descriptions (Continued) 5 SSC_DIS I Spread Spectrum Disable. This pin allows disabling of the spread spectrum feature on the output clocks. Connect to 1 disable spread spectrum on all outputs. Connect to GND to enable spread spectrum. Note that the maximum voltage level on this pin must not exceed 1 resistor voltage divider is recommended when controlled by a signal greater than 1 ...

Page 20

... Si5356 Table 8. Si5356 Pin Descriptions (Continued) 20 VDDOA VDD Clock Output Bank A Supply Voltage. Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V sup- ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK0/1 are not used, this pin must be tied to pin 7 and/or pin 24. ...

Page 21

... R = Tape & Reel (ordering option) When ordering non-tape & reel shipment media, contact your sales representative for more information. Preliminary Rev. 0.3 Si5356 product revision xxxxx = 5-digit custom code assigned to each unique device configuration. Leave xxxxx blank for standard factory default configuration (Si5356A-A-GMR) 21 ...

Page 22

... Si5356 7. Package Outline: 24-Lead QFN Figure 11. 24-Lead Quad Flat No-Lead (QFN) Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. ...

Page 23

... A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Table 10. PCB Land Pattern Min Nom 2.50 2.55 2.50 2.55 0.20 0.25 0.75 0.80 3.90 3.90 0.50 Preliminary Rev. 0.3 Si5356 Max 2.60 2.60 0.30 0.85 23 ...

Page 24

... Xxxxxx Line 2 RTTTTT Line 3 Circle with 0. mm diameter; Line 4 left-justified YYWW 24 Si5356 Xxxxxx RTTTTT YYWW Description Base part number Frequency and configuration code (e.g etc.) xxxxx = Optional NVM code for custom factory-programmed devices; (characters are not included for blank devices). See Section “ Document Change List” section in data sheet for more information ...

Page 25

... Added Section “3.1. Overview”  Updated Section “3.2. Input Configuration”  Updated Section “3.4. Frequency Configuration”  Added Section “3.5. Configuring the Si5356”  Added Section “4. Si5356 Registers”  Added Section “9. Top Marking”  ...

Page 26

... Si5356 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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