AC164112 Microchip Technology, AC164112 Datasheet - Page 297

• Manufacturer Part Number: AC164112
• Description: VOLTAGE LIMITER MPLAB ICD2 VPP
• Manufacturer: Microchip Technology

Specifications of AC164112

• Accessory Type: Voltage Limiter
• Product: Cable Assemblies
• Features: Programming And Debugging The Latest PIC12/PIC16/PIC18 Products
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPLAB®
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: MPLAB ICD 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Special Function Registers ................................................. 20
Special Function Registers (SFRs) ..................................... 24
SPI Mode .......................................................................... 173
SSP ................................................................................... 167
SSPADD Register ............................................................... 25
SSPBUF Register ............................................................... 24
SSPCON Register .............................................. 24, 174, 186
SSPEN bit ................................................................. 174, 186
SSPM bits ................................................................. 174, 186
SSPMSK Register............................................................... 25
SSPOV bit ................................................................. 174, 186
SSPSTAT Register ............................................. 25, 175, 187
STATUS Register ............................................................... 27
Synchronous Serial Port Enable bit (SSPEN)........... 174, 186
Synchronous Serial Port Mode Select bits (SSPM) .. 174, 186
T
T1CON Register ......................................................... 24, 124
T1GCON Register............................................................. 125
T2CON Register ................................................. 24, 128, 176
Thermal Considerations .................................................... 220
Time-out Sequence............................................................. 38
Timer0 ............................................................................... 111
Timer1 ............................................................................... 115
Timer2
Timers
© 2009 Microchip Technology Inc.
Associated Registers ................................................ 176
Typical Master/Slave Connection ............................. 167
I
Master Mode ............................................................. 169
SPI Mode .................................................................. 167
Typical SPI Master/Slave Connection....................... 167
TMR1ON Bit.............................................................. 125
Associated Registers ................................................ 113
Interrupt..................................................................... 113
Operation .......................................................... 111, 116
Specifications............................................................ 229
Associated registers.................................................. 126
Asynchronous Counter Mode ................................... 117
Interrupt..................................................................... 120
Modes of Operation .................................................. 116
Module On/Off (TMR1ON Bit)................................... 125
Operation During Sleep ............................................ 120
Oscillator ................................................................... 117
Prescaler................................................................... 117
Specifications............................................................ 229
Timer1 Gate
TMR1H Register ....................................................... 115
TMR1L Register........................................................ 115
Associated registers.................................................. 128
Timer1
2
C Mode................................................................... 177
Acknowledge .................................................... 178
Addressing ........................................................ 179
Clock Stretching................................................ 184
Clock Synchronization ...................................... 185
Firmware Master Mode ..................................... 184
Hardware Setup ................................................ 177
Multi-Master Mode ............................................ 184
Reception.......................................................... 180
Sleep Operation ................................................ 185
Start/Stop Conditions ........................................ 178
Transmission .................................................... 182
Slave Mode ....................................................... 171
Reading and Writing ......................................... 117
Selecting Source............................................... 118
T1CON.............................................................. 124
PIC16F72X/PIC16LF72X
Timing Diagrams
Timing Parameter Symbology .......................................... 221
Timing Requirements
TMR0 Register.................................................................... 24
TMR1H Register ................................................................. 24
TMR1L Register.................................................................. 24
TMR2 Register.................................................................... 24
TMRO Register................................................................... 26
TRISA ................................................................................. 54
TRISA Register............................................................. 25, 54
TRISB ................................................................................. 62
TRISB Register............................................................. 25, 63
TRISC ................................................................................. 73
TRISC Register............................................................. 25, 73
TRISD ................................................................................. 80
TRISD Register............................................................. 25, 81
TRISE ................................................................................. 84
TRISE Register............................................................. 25, 85
TXREG ............................................................................. 147
TXREG Register ................................................................. 24
TXSTA Register.......................................................... 25, 154
Timer2
A/D Conversion ........................................................ 231
A/D Conversion (Sleep Mode).................................. 232
Asynchronous Reception.......................................... 152
Asynchronous Transmission .................................... 148
Asynchronous Transmission (Back-to-Back)............ 148
Brown-out Reset (BOR)............................................ 227
Brown-out Reset Situations ........................................ 37
CLKOUT and I/O ...................................................... 225
Clock Synchronization .............................................. 185
Clock Timing............................................................. 222
Enhanced Capture/Compare/PWM (ECCP)............. 230
I
I
I
I
I
INT Pin Interrupt ......................................................... 44
Reset, WDT, OST and Power-up Timer ................... 226
Slave Select Synchronization ................................... 173
SPI Master Mode...................................................... 170
SPI Master Mode (CKE = 1, SMP = 1) ..................... 234
SPI Mode (Slave Mode with CKE = 0)...................... 172
SPI Mode (Slave Mode with CKE = 1)...................... 172
SPI Slave Mode (CKE = 0) ....................................... 235
SPI Slave Mode (CKE = 1) ....................................... 235
Synchronous Reception (Master Mode, SREN) ....... 162
Synchronous Transmission ...................................... 160
Synchronous Transmission (Through TXEN) ........... 160
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 229
Timer1 Incrementing Edge ....................................... 120
USART Synchronous Receive (Master/Slave) ......... 233
USART Synchronous Transmission (Master/Slave). 232
Wake-up from Interrupt............................................. 194
I
I2C Bus Start/Stop Bits............................................. 237
SPI Mode.................................................................. 236
2
2
2
2
2
2
C Bus Data............................................................. 237
C Bus Start/Stop Bits ............................................. 236
C Reception (7-bit Address)................................... 180
C Slave Mode with SEN = 0 (Reception,
C Transmission (7-bit Address) ............................. 182
C Bus Data............................................................. 238
T1GCON........................................................... 125
T2CON ............................................................. 128
10-bit Address) ................................................. 181
Case 1 ................................................................ 39
Case 2 ................................................................ 39
Case 3 ................................................................ 39
DS41341E-page 297