AC164112 Microchip Technology, AC164112 Datasheet - Page 188
![VOLTAGE LIMITER MPLAB ICD2 VPP](/photos/8/95/89583/ac164112_sml.jpg)
AC164112
Manufacturer Part Number
AC164112
Description
VOLTAGE LIMITER MPLAB ICD2 VPP
Manufacturer
Microchip Technology
Datasheet
1.AC164112.pdf
(302 pages)
Specifications of AC164112
Accessory Type
Voltage Limiter
Product
Cable Assemblies
Features
Programming And Debugging The Latest PIC12/PIC16/PIC18 Products
Development Tool Type
Hardware - Eval/Demo Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MPLAB®
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With
MPLAB ICD 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AC164112
Manufacturer:
Microchip Technology
Quantity:
135
- Current page: 188 of 302
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PIC16F72X/PIC16LF72X
REGISTER 17-5:
REGISTER 17-6:
TABLE 17-7:
DS41341E-page 188
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPMSK
SSPSTAT
TRISC
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Name
R/W-1
MSK7
R/W-0
ADD7
2:
(2)
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I
mode.
Maintain these bits clear in I
Accessible only when SSPM<3:0> = 1001.
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
Synchronous Serial Port (I
TMR1GIE
TMR1GIF
TRISC7
SMP
WCOL
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I
0 = The received address bit ‘0’ is not used to detect I
All other SSP modes: this bit has no effect.
ADD<7:0>: Address bits
Received address
Bit 7
GIE
2
C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):
REGISTERS ASSOCIATED WITH I
(1)
R/W-1
MSK6
R/W-0
ADD6
SSPMSK: SSP MASK REGISTER
SSPADD: SSP I
SSPOV
TRISC6
CKE
PEIE
ADIF
ADIE
Bit 6
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-1
R/W-0
MSK5
ADD5
TRISC5
SSPEN
2
RCIF
RCIE
2
2
Bit 5
T0IE
C mode.
2
D/A
C mode) Address Register
C mode) Address Mask Register
C Slave Mode, 10-bit Address
2
C ADDRESS REGISTER
TRISC4 TRISC3
Bit 4
INTE
TXIF
TXIE
CKP
P
R/W-1
MSK4
R/W-0
ADD4
SSPM3
SSPIF
SSPIE
RBIE
Bit 3
S
2
C OPERATION
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R/W-0
CCP1IE
MSK3
ADD3
CCP1IF
TRISC2
SSPM2
2
Bit 2
T0IF
R/W
C address match
2
C address match
TMR2IE
TMR2IF
TRISC1
SSPM1
Bit 1
INTF
UA
R/W-1
MSK2
R/W-0
ADD2
2
C address match
2
C address match
TMR1IF
TMR1IE
TRISC0
SSPM0
RBIF
Bit 0
BF
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
POR, BOR
R/W-1
R/W-0
MSK1
ADD1
Value on
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
Value on
all other
R/W-1
MSK0
R/W-0
ADD0
Resets
bit 0
bit 0
2
C
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