L6701 STMicroelectronics, L6701 Datasheet - Page 26

• Manufacturer Part Number: L6701
• Description: IC CTRLR 3PH VR10/9/K8 PWRSO-36
• Manufacturer: STMicroelectronics

Specifications of L6701

• Applications: Controller, Intel VR9, VR10, K8
• Voltage - Input: 12V
• Number Of Outputs: 3
• Voltage - Output: 0.8 ~ 1.85 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-PowerSOIC
• Output Voltage: 0.8 V to 1.85 V
• Output Current: 1.5 A
• Switching Frequency: 110 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11 Dynamic VID Transitions
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Dynamic VID Transitions
L6701 is able to manage Dynamic VID Code changes in all its operative modes (VR10, K8 and
also VR9) so allowing Output Voltage modification during normal device operation. PGOOD
(when applicable), OVP and UVP signals are masked during every VID transition and they are
re-activated after the transition finishes with a 32 clock cycles delay to prevent from false
triggering.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current
needs to be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the over current threshold. In the previous relationship, dV
selected DAC LSB (12.5mV for VR10 DAC or 25mV for both VR9 and K8 DACs) and T
the time interval between each LSB transition (typically externally driven). Overcoming the OC
threshold during the dynamic VID causes the device to enter the constant current limitation
slowing down the output voltage dV/dt also causing the failure in the D-VID test.
Figure 11. Dynamic VID Transitions
L6701 checks for VID code modifications (See
additional DVID-clock and waits for a confirmation on the following falling edge. Once the new
code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition, VID
code changes are ignored; the device re-starts monitoring VID after the transition has finished
on the next rising edge available. VID-clock frequency (F
selected: for VR10 Mode it is equal to three times the system switching frequency programmed
for each phase (F
and K8, this frequency is lowered to F
Int. Reference
VID Clock
VID [0,5]
V out
T
DVID
Vout Slope Controlled by internal
DVID
T sw
x 4 Step VID Transition
DVID-Clock Oscillator
= 3 x F
SW
I
) to assure compatibility with the specifications while, for VR9
D VID
–
DVID
=
C
= F
OUT
SW
Figure
⋅
T
VID
dV
.
Vout Slope Controlled by external
OU T
4 x 1 Step VID Transition
11) on the rising edge of an internal
⁄
driving circuit (T
dT
DVID
VI D
) depends on the operative mode
VID
)
OUT
VID
L6701
is the
t
t
t
t
is