ADM1034ARQZ-R7 ON Semiconductor, ADM1034ARQZ-R7 Datasheet - Page 27

• Manufacturer Part Number: ADM1034ARQZ-R7
• Description: IC THERM/FAN SPEED CTLR 16-QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1034ARQZ-R7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XOR Tree Test Mode
useful for in circuit test equipment at board level testing. By
applying stimulus to the pins included in the XOR test, it is
possible to detect opens or shorts on the system board.
Figure 43 shows the signals that are exercised in the XOR
tree test mode. The XOR tree test is enabled by setting the
XOR bit (Bit 3) in Configuration 4 Register (0x04).
DRIVE2
Table 31. ADM1034 Registers
TACH1
0x0C/8C
0x0D/8D
Address
0x0A/8A
0x0B/8B
0x0E/8E
0x0F/8F
0x00/80
0x01/81
0x02/82
0x03/83
0x04/84
0x05/85
0x06/86
0x07/87
0x08/88
0x09/89
The ADM1034 includes an XOR tree test mode. This is
THERM
FAN_FAULT/REF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 43. XOR Tree Test
LOCATION
#Bytes/Block
Read
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Conversion
Rate
Fault Queue
Fan Behavior
Mask 1
Mask 2
Mask 3
Local High
Limit
Local Low
Limit
Local THERM
Limit
Remote 1
High Limit
Remote 1 Low
Limit
Description
ALERT
Bit 7
Table
#FP2
REF
RES
RES
RES
/SW
R R
F1S
FF/
Off
LH
F2
7
7
7
7
7
7
#FP2
Bit 6
Lock
RES
RES
RES
RES
% T
Off
FA
F1
LL
6
6
6
6
6
6
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DRIVE1
#FP2
Bit 5
SDA
RES
RES
RES
R1H
RES
F2S
% T
CS
5
5
5
5
5
5
27
#FP2
Bit 4
RES
RES
RES
RES
SCL
% T
R1L
% T
CS
4
4
4
4
4
4
Lock Bit
(Address 0x01) makes all the lockable registers read−only.
These registers remain read−only until the ADM1034 is
powered down and back up again. For more information on
which registers are lockable, see Table 31.
SW Reset
Register 2 (Address 0x02) resets all software resettable bits
to their default value. For more information on resetting
registers and their default values, see Table 31 to Table 71.
Setting the Lock bit (Bit 6) of Configuration Register 1
Setting the Software Reset bit (Bit 0) of Configuration
ALERT
#FP1
Conv
Bit 3
XOR
R1D
RES
LUT
D2B
FQ
TA
3
3
3
3
3
3
TIMER
R2TM
#FP1
Conv
Bit 2
RES
D2B
R2H
D/L
FQ
TS
2
2
2
2
2
2
R1TM
#FP1
Conv
Bit 1
D1B
RES
RES
R2L
Avg
BD
FQ
1
1
1
1
1
1
Reset
#FP1
Conv
Bit 0
RES
RES
Mon
LTM
D1B
R2D
FQ
0
0
0
0
0
0
Default
0x8B
0x8B
0x20
0x01
0x84
0x44
0x00
0x07
0x01
0x09
0x52
0x18
0x00
0x54
0x95
0x54
Lock−
able?
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
N