ADM1034ARQZ-R7 ON Semiconductor, ADM1034ARQZ-R7 Datasheet - Page 12

• Manufacturer Part Number: ADM1034ARQZ-R7
• Description: IC THERM/FAN SPEED CTLR 16-QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1034ARQZ-R7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operations
write operations. The ADM1034 supports send byte, write
byte, and block byte SMBus write protocols. The following
abbreviations are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
Send Byte
single−command byte to a slave device as follows:
register address to the APR for a subsequent read from the
same address. (See Figure 24.) The user may be required to
read data from the register immediately after setting up the
address. If so, the master can assert a repeat start condition
immediately after the final ACK and carry out a single byte
read without asserting an intermediate stop condition.
Write Byte
address and one data byte to the slave device as follows:
The SMBus specifications define protocols for read and
In this operation, the master device sends a
The ADM1034 uses the send byte operation to write a
In this operation, the master device sends a register
1. The master device asserts a start condition on
2. The master sends a 7−bit address followed by the
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and
1. The master asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The MSB of
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end
SDA.
write bit (low).
the transaction ends.
by a write bit (low).
the register address should equal 0 for a write byte
operation. If the MSB equals 1, a block write
operation takes place.
the transaction.
S
ADDRESS
Figure 20. Send Byte
SLAVE
W A
ADDRESS
REG
A P
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Block Write
to a slave address as follows. A maximum of 32 bytes can be
written.
Read Operations
Receive Byte
The register address must be set up prior to this, with the
MSB at 0 to read a single byte. In this operation, the master
device receives a single byte from a slave device as follows:
a single byte from a register whose address has previously
been set by a send byte or write byte operation.
In this operation, the master device writes a block of data
This is useful when repeatedly reading a single register.
In the ADM1034, the receive byte protocol is used to read
S
10. The master asserts a stop condition on SDA to end
ADDRESS
1. The master asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The register
5. The slave asserts ACK on SDA.
6. The master sends the byte count.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each byte.
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master sends NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
SLAVE
by a write bit (low).
address sets up the address pointer register and
determines whether a block write (MSB = 1) or a
byte write (MSB = 0) takes place.
the transaction.
SDA.
by the read bit (high).
the transaction ends.
S
W A
ADDRESS
Figure 21. Write Byte Operation
Figure 22. Block Write to RAM
SLAVE
S
REGISTER
ADDRESS
Figure 23. Receive Byte
ADDRESS
SLAVE
W A
A
ADDRESS
COUNT
BYTE
R A
REG
A
DATA
DATA 1
A
DATA
A P
A
DATA 2
A
A
P
DATA N
A P