ADM1026JSTZ-REEL ON Semiconductor, ADM1026JSTZ-REEL Datasheet - Page 46

• Manufacturer Part Number: ADM1026JSTZ-REEL
• Description: IC CNTRL SYS REF/EEPROM 48-LQFP
• Manufacturer: ON Semiconductor

Specifications of ADM1026JSTZ-REEL

• Function: Hardware Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 100°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Full Temp Accuracy: +/- 3 C
• Digital Output - Bus Interface: Serial (2-Wire)
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. GPIO status bits can be written only when a GPIO pin is configured as output. Read−only otherwise.
Table 46. Register 24h, Status Register 5 (Power−On Default, 00h)
Bit
0
1
2
3
4
5
6
7
GPIO0 Status = 0
GPIO1 Status = 0
GPIO2 Status = 0
GPIO3 Status = 0
GPIO4 Status = 0
GPIO5 Status = 0
GPIO6 Status = 0
GPIO7 Status = 0
Name
(Note 1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 1.)
When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 1.)
When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 1.)
When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 1.)
When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 1.)
When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 1.)
When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 1.)
When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 1.)
When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 2.)
When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 2.)
When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 2.)
When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 2.)
When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 2.)
When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 2.)
When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 2.)
When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 2.)
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