CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 92

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

CP2400/1/2/3
13. Timers
CP2400/1/2/3 devices include two 16-bit auto-reload timers. These timers can be used to measure time intervals
and generate periodic interrupt requests. Both timers can be clocked from the system clock source divided by 12.
Timer 1 has an additional SmaRTClock divided by 8 input and capture mode that can be used to measure the
SmaRTClock oscillation frequency with respect to the system clock. When SMBus SCL low timeout is enabled,
Timer 0 becomes unavailable for general purpose use. Timer 0 is enabled on reset.
13.1. Timer 0
Timer 0 is a 16-bit timer formed by two 8-bit SFRs: TMR0L (low byte) and TMR0H (high byte). Timer 0 operates in
16-bit auto-reload mode and is clocked by the system clock divided by 12. As the 16-bit timer register increments
and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 0 reload registers (TMR0RLH and TMR0RLL)
is loaded into the Timer 0 register as shown in Figure 13.1, and the Timer 0 Overflow Flag (INT1.2) is set. If
Timer 0 interrupts are enabled (if INT1EN.2 is set), an interrupt will be generated on each Timer 0 overflow.
Additionally, if Timer 0 interrupts are enabled and the TF0LEN bit is set (TMR0CN.5), an interrupt will be generated
each time the lower 8 bits (TMR0L) overflow from 0xFF to 0x00.
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S Y S C LK / 12
T R 0
Figure 13.1. Timer 0 Block Diagram
Rev. 1.0
T M R 0R LL T M R 0R L H
T M R 0L
Lo w B yte
O verflo w
T M R 0H
R e loa d
T o S M B us
T o Interrup t