CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 60

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

CP2400/1/2/3
10. Port Input/Output
CP2400/1/2/3 devices have 36 (48-pin packages) or 20 (32-pin packages) multi-function I/O pins. Port pins are
organized as byte-wide ports and may be used for general purpose I/O, generating a Port Match interrupt, or for an
analog function (e.g., LCD).
Note: The port match functionality described in this chapter only applies when the device is awake (Normal and Idle Power
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as digital
push-pull outputs, current is sourced from the V
operating modes and the electrical specifications chapter for detailed electrical specifications. Figure shows a
block diagram of the Port I/O for the 48-pin packaged devices. The 32-pin packaged devices are functionally the
same, however, they have less I/O. Refer to the System Overview for a detailed block diagram of 32-pin devices.
60
Modes). Refer to the Power Modes chapter for information on port match wake-up from ULP or shutdown mode.
P0
P1
P2
P3
P4
(P0.0-P0.7)
(P1.0-P1.7)
(P0.0-P0.7)
(P3.0-P3.7)
(P4.0-P4.3)
36
8
8
8
8
4
Figure 10.1. Port I/O Diagram
Rev. 1.0
DD
supply. See Section 10.1 for more information on Port I/O
Configuration
Mapping
Registers
Logic
Port
Port Match
8
8
8
8
4
Cells
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
I/O
P0
P1
P2
P3
P4
PnMDO, PnMDI
Registers
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.3