CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 37

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

6.3.
The CP2400/1/2/3 internal registers are grouped into categories based on function. The memory map is organized
to minimize register access time, by sequentially locating registers that can be read or written with a single block
read or write. Table 6.3 shows the register memory map for all registers available on the device.
SmaRTClock Registers
RTCKEY
RTCADR
RTCDAT
Interrupt Mask and Clocking Registers
INT0EN
INT1EN
CLKSL
IOSCCN
REVID
Interrupt Status Registers
INT0RD
INT1RD
ULPST
INT0
INT1
Timer 0 and Timer 1 Registers
TMR0RLL
TMR0RLH
TMR0L
TMR0H
TMR0CN
TMR1RLL
TMR1RLH
TMR1L
TMR1H
TMR1CN
SMBus Registers
SMBCF
ULP/LCD0 Data Registers
LCD0BLINK
ULPMEM00
ULPMEM01
ULPMEM02
Register
Internal Registers
Address
0x0C
0x0A
0x0B
0x81
0x82
0x83
0x30
0x31
0x32
0x33
0x34
0x40
0x41
0x42
0x43
0x44
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x68
0x80
Table 6.3. Internal Register Memory Map
RTC0 Lock and Key
Internal Oscillator Control
Timer 0 Reload Register Low Byte
Timer 0 Reload Register High Byte
Timer 0 Low Byte
Timer 0 High Byte
Timer 0 Control
Timer 1 Reload Register Low Byte
Timer 1 Reload Register High Byte
Timer 1 Low Byte
Timer 1 High Byte
Timer 1 Control
LCD0 Segment Blink
ULP Memory Byte 0
ULP Memory Byte 1
ULP Memory Byte 2
RTC0 Indirect Address
RTC0 Indirect Data
Interrupt Enable Register 0
Interrupt Enable Register 1
Clock Select
Revision Identifier
Interrupt Status Register 0 (read-only)
Interrupt Status Register 1 (read-only)
Ultra Low Power Status
Interrupt Status Register 0 (self-clearing)
Interrupt Status Register 1 (self-clearing)
SMBus Configuration
Rev. 1.0
Description
CP2400/1/2/3
Preserved
N
N
N
N
N
N
N
Y
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
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