CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 43

• Manufacturer Part Number: CP2401-GQ
• Description: IC LCD DRIVER 48TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2401-GQ

• Package / Case: 48-TQFP, 48-VQFP
• Display Type: LCD
• Configuration: 128 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1860

SFR Definition 7.3. INT0EN: Interrupt Enable Register 0
Address = 0x30
Name
Reset
7:6
2:1
Bit
Type
5
4
3
0
Bit
ERTCFAIL Enable SmaRTClock Fail Interrupt.
Reserved Read = varies. Write = must write 0b.
EPMINT
Unused
EALRM
Unused
Name
R/W
7
1
Read = 11b. Write = don’t care.
Enable SmaRTClock Alarm Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm Events.
This bit sets the masking of the SmaRTClock Oscillator Fail interrupt.
0: Disable SmaRTClock Oscillator Fail interrupt.
1: Enable interrupt requests generated by SmaRTClock Oscillator Failure.
Read = 11b. Write = don’t care.
Enable Port Match Interrupt.
This bit sets the masking of Port Match Interrupt.
0: Disable Port Match Interrupt.
1: Enable interrupt requests generated by Port Match events.
R/W
6
1
Reserved
R/W
5
1
Rev. 1.0
EALRM
R/W
4
1
Function
ERTCFAIL
R/W
3
0
R/W
2
1
CP2400/1/2/3
R/W
1
1
EPMINT
R/W
0
1
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