CP2401-GQ Silicon Laboratories Inc, CP2401-GQ Datasheet - Page 65

IC LCD DRIVER 48TQFP

CP2401-GQ

Manufacturer Part Number
CP2401-GQ
Description
IC LCD DRIVER 48TQFP
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of CP2401-GQ

Package / Case
48-TQFP, 48-VQFP
Display Type
LCD
Configuration
128 Segment
Interface
I²C, SMBus
Current - Supply
620µA
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Data Ram Size
256 B
Interface Type
I2C, SMBus
Maximum Clock Frequency
25 MHz
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1860

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CP2401-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
CP2401-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
CP2401-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
CP2400/1/2/3
10.4. Registers for Accessing and Configuring Port I/O
All Port I/O are accessed and configured through registers. When writing to a Port, the value written to the PnOUT
register is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input
pins are returned in the PnIN. If the PnOUT register is read, the value returned will be the value of the output latch,
not the logic level of the port pad. The PnIN register is read only.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDI). Each Port cell can be
configured for analog or digital I/O. The output driver characteristics of the digital I/O pins are defined using the Port
Output Mode registers (PnMDO). Each Port Output driver can be configured as either open drain or push-pull. To
configure a pin as a digital input, configure it as an open drain output and write 1 to its port latch.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRIVE) registers. The default
is low drive strength. See Table 3.2 on page 13 for the difference in output drive strength between the two modes.
Rev. 1.0
65

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