LH28F008SCT-L85 Sharp Microelectronics, LH28F008SCT-L85 Datasheet - Page 27

• Manufacturer Part Number: LH28F008SCT-L85
• Description: IC FLASH 8MBIT 85NS 40TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F008SCT-L85

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1835; F008SCTL85; LHF08CH1

sharp
5.5 V
Block erase, byte write and lock-bit configuration are
not guaranteed if V
range, V
RP#≠V
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP#
transitions to V
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-down.
The aborted operation may leave data partially
altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V
register.
The CUI latches commands issued by system
software and is not altered by V
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
V
After block erase, byte write, or lock-bit configuration,
even after V
must be placed in read array mode via the Read
Array command if subsequent access to the memory
array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration
power-up, the device is indifferent as to which power
CC
transitions below V
IH
CC
CC
or V
, V
falls outside of a valid V
PP
PP
HH
IL
during
transitions down to V
, RP# Transitions
. If V
during block erase, byte write, or
PP
falls outside of a valid V
LKO
PP
power
.
error is detected, status
PP
transitions.
IL
or CE# transitions
CC2/3/4
clear the status
PPLK
, the CUI
range, or
PPH1/2/3
Upon
LHF08CH1
supply (V
resets the CUI to read array mode at power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either to V
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=V
5.7 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
In
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to V
standby or sleep modes. If access is again needed,
the devices can be read following the t
t
raised to V
and Write Operations and Figures 15, 16 and 17 for
more information.
PHWL
addition,
wake-up cycles required after RP# is first
PP
IH
CC
or V
IL
. See AC Characteristics− Read Only
regardless of its control inputs state.
deep
voltages above V
CC
) powers-up first. Internal circuitry
power-down
IH
LKO
will inhibit writes.
mode
when V
PHQV
Rev. 1.3
ensures
PP
and
24
is
IL