LH28F008SCT-L85 Sharp Microelectronics, LH28F008SCT-L85 Datasheet - Page 16

• Manufacturer Part Number: LH28F008SCT-L85
• Description: IC FLASH 8MBIT 85NS 40TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F008SCT-L85

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1835; F008SCTL85; LHF08CH1

sharp
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
can
V
block contents are protected against erasure. If block
erase is attempted while V
will be set to "1". Successful block erase requires that
the corresponding block lock-bit be cleared or, if set,
that RP#=V
corresponding block lock-bit is set and RP#=V
SR.1 and SR.5 will be set to "1". Block erase
operations with V
results and should not be attempted.
4.6 Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the byte write sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect the
completion of the byte write event by analyzing the
RY/BY# pin or status register bit SR.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for "1"s that do not
successfully write to "0"s. The CUI remains in read
status register mode until it receives another
command.
Reliable
V
this high voltage, memory contents are protected
against byte writes. If byte write is attempted while
V
set to "1". Successful byte write requires that the
PP
CC
PP
=V
≤V
=V
PPLK
PPH1/2/3
CC2/3/4
only
byte
, status register bits SR.3 and SR.4 will be
HH
. In the absence of this high voltage,
. If block erase is attempted when the
and V
occur
writes
IH
PP
<RP#<V
=V
when
PPH1/2/3
can
PP
≤V
HH
PPLK
V
only
. In the absence of
CC
produce spurious
=V
, SR.3 and SR.5
CC2/3/4
occur
when
and
LHF08CH1
IH
,
corresponding block lock-bit be cleared or, if set, that
RP#=V
corresponding block lock-bit is set and RP#=V
SR.1 and SR.4 will be set to "1". Byte write
operations with V
results and should not be attempted.
4.7 Block Erase Suspend Command
The
block-erase interruption to read or byte-write data in
another block of memory. Once the block-erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block
erase sequence at a predetermined point in the
algorithm. The device outputs status register data
when read after the Block Erase Suspend command
is written. Polling status register bits SR.7 and SR.6
can determine when the block erase operation has
been suspended (both will be set to "1"). RY/BY# will
also transition to V
the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Byte Write command sequence can
also be issued during erase suspend to program data
in other blocks. Using the Byte Write Suspend
command (see Section 4.8), a byte write operation
can also be suspended. During a byte write operation
with block erase suspended, status register bit SR.7
will return to "0" and the RY/BY# output will transition
to V
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and
RY/BY# will return to V
command is written, the device automatically outputs
status register data when read (see Figure 7). V
must remain at V
for block erase) while block erase is suspended. RP#
must also remain at V
used for block erase). Block erase cannot resume
until byte write operations initiated during block erase
suspend have completed.
OL
Block
. However, SR.6 will remain "1" to indicate
HH
. If byte write is attempted when the
Erase
PPH1/2/3
OH
IH
<RP#<V
. Specification t
IH
Suspend
OL
or V
. After the Erase Resume
(the same V
HH
HH
(the same RP# level
command
produce spurious
WHRH2
PP
level used
Rev. 1.3
defines
allows
13
IH
PP
,