MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 9

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
LENGTH
Page (y)
1. For full-page accesses: y = 256.
2. For a burst length of two, A1–A7 select the block-of-
3. For a burst length of four, A2–A7 select the block-of-
4. For a burst length of eight, A3–A7 select the block-of-
5. For a full-page burst, the full row is selected and A0–A7
6. Whenever a boundary of the block is reached within a
BURST
Full
two burst; A0 selects the starting column within the
block.
four burst; A0–A1 select the starting column within the
block.
eight burst; A0–A2 select the starting column within
the block.
select the starting column.
given sequence above, the following access wraps
within the block.
2
4
8
A2 A1 A0
STARTING
0
0
0
0
1
1
1
1
ADDRESS
n = A0–A7
COLUMN
(location
0-y)
Burst Definition
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn+4..., …Cn-1,
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
ORDER OF ACCESSES WITHIN
SEQUENTIAL
Cn+2, Cn+3,
Cn, Cn+1,
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
A BURST
INTERLEAVED
Not Supported
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
9
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 4.
7. For a burst length of one, A0–A7 select the unique col-
The remaining (least significant) address bit(s) is
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
** BA1, BA0 = “0, 0”
to prevent Extended
Figure 4: Mode Register Definition
umn to be accessed, and mode register bit M3 is
ignored.
Mode Register.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
to ensure compatibility
with future devices.
Reserved**
*Should program
13
BA1
M13
M10 = “0, 0”
12
BA0
M12
Reserved* WB
11
M11
A11
10
A10
M10
M9
0
1
9
M9
A9
Op Mode
M8
8
A8
7
M7 M6
A7 A6
Programmed Burst Length
M8
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
MOBILE SDRAM
5
M5
A5
M7
©2003 Micron Technology, Inc. All rights reserved.
0
-
4
M4
A4
BT
M3
M6-M0
Defined
0
1
3
M3
A3
-
M6
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M2
M1
M5
A2
64Mb: x16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
M1
0
M0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Burst Length
Address Bus
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8