MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 22

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER-DOWN
dent with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maxi-
mum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
Down.
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Figure 23: Terminating a WRITE Burst
COMMAND
CLK
CKE
Power-down occurs if CKE is registered low coinci-
The power-down state is exited by registering a NOP
All banks idle
Enter power-down mode.
COMMAND
DQMs are LOW.
t CKS
ADDRESS
Figure 22: Power-Down
NOP
CLK
DQ
TRANSITIONING DATA
Input buffers gated off
BANK,
WRITE
COL n
D
T0
n
IN
t
CKS). See Figure 22, Power-
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
Exit power-down mode.
TERMINATE
BURST
T1
> t CKS
COMMAND
(ADDRESS)
DON’T CARE
NOP
(DATA)
NEXT
T2
ACTIVE
t RCD
t RAS
t RC
22
DEEP POWER-DOWN
ings feature achieved by shutting off the power to the
entire memory array of the device. Data on the mem-
ory array will not be retained once deep power down
mode is executed. Deep power down mode is entered
by having all banks idle then CS# and WE# held low
with RAS# and CAS# high at the rising edge of the
clock, while CKE is low. CKE must be held low during
deep power-down.
be asserted high. After exiting, the following sequence
is needed in order to enter a new command. Maintain
NOP input conditions for a minimum of 100us. Issue
PRECHARGE commands for all banks. Issue eight or
more AUTOREFRESH commands. The values of the
mode register and extended mode register will be
retained upon exiting deep power-down.
CLOCK SUSPEND
access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
Deep power down mode is a maximum power sav-
In order to exit deep power down mode, CKE must
The clock suspend mode occurs when a column
For each positive clock edge on which CKE is sam-
Figure 24: PRECHARGE Command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A0-A9, A11
BA0,1
RAS#
CAS#
WE#
CKE
CLK
A10
CS#
HIGH
VALID ADDRESS
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Bank Selected
All Banks
ADDRESS
BANK
64Mb: x16
DON’T CARE