MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 34

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no
13. I
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured for 1.8V at 0.9V with equivalent
= 25°C; pin under test biased at 1.4V. f = 1 MHz.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range (-25°C
+85°C for standard parts; -40°C T
parts) is ensured.
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
load:
t
the open circuit condition; it is not a reference to
V
t
timing referenced to V
the input transition time is longer than
then the timing is referenced at V
(MIN) and no longer at the V
more than once every two clocks and are other-
wise at valid V
properly initialized.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
OH
SS
IH
and V
and V
is dependent on output loading and cycle
specifications are tested after the device is
or V
DD
OL
Q must be powered up simultaneously.
SS
IL
. The last valid data element will meet
Q must be at same potential.) The two
(or between V
IH
Q
or V
DD
IL
tests have V
t
levels.
REF refresh requirement is
IH
/2 = crossover point. If
t
IL
SS
T = 1ns.
IH
.
DD
and V
30pF
/2 crossover point.
, V
IL
IL
DD
A
IH
(MAX) and V
and V
Q = +1.8V; T
) in a mono-
+85°C for IT
t
T (MAX),
IH
, with
T
A
DD
IH
A
34
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8, CL = 2,
33. CKE is HIGH during refresh command period
34. Deep power down current is a nominal value at
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
width
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
clock delay, after the last WRITE is executed. May
not exceed limit set for precharge mode.
t
anteed by design.
= 9.6ns.
t
actually a nominal value and does not result in a
fail value.
25°C. The parameter is not tested.
AC for -8 at CL = 3 with no load is 7ns and is guar-
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
t
overshoot: V
WR, and PRECHARGE commands). CKE may
DD
IL
current will increase or decrease propor-
t
t
RP) begins at 7ns for -8 after the first
3ns, and the pulse width cannot be
CK = 8ns for -8 and
(MIN) = -2V for a pulse width 3ns.
t
CK = 9.6ns. For -10, CL = 3 and
IH
(MAX) = V
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
t
t
WR plus
WR.
t
DD
t
CKS; clock(s) speci-
CK = 9.6ns for -10.
64Mb: x16
Q + 2V for a pulse
t
DD
RP; clock(s)
6 limit is
IL
under-
t
CK