MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 5

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
dynamic
67,108,864-bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 16,777,216-bit banks is orga-
nized as 4,096 rows by 256 columns by 16 bits.
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
The Micron
Read and write accesses to the SDRAM are burst ori-
Figure 2: Part Numbering Diagram
54-ball VFBGA (8mm x 8mm)
54-ball VFBGA (8mm x 8mm) Lead-Free
V
1.8/1.8V
DD
/V
MT48
DD
Q
Example Part Number: MT48H4M16LF-8 IT
Configuration
random-access
4 Meg x16
V
Package
V
DD
®
DD
Q
/
H
64Mb SDRAM is a high-speed CMOS,
Configuration
4M16LF
Package
B4
F4
memory
–
Speed
-10
-8
None
IT
Speed Grade
Operating Temp
containing
8ns
9.6ns
Temp
Extended
Industrial
5
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0–A11 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, Deep Power-
Down Mode. All inputs and outputs are LVTTL-com-
patible.
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.
The SDRAM provides for programmable read or
The 64Mb SDRAM uses an internal pipelined archi-
The 64Mb SDRAM is designed to operate in 1.8V,
SDRAMs offer substantial advances in DRAM oper-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16