LH28F640SPHT-PTL12 Sharp Microelectronics, LH28F640SPHT-PTL12 Datasheet - Page 15

• Manufacturer Part Number: LH28F640SPHT-PTL12
• Description: IC FLASH 64MBIT 120NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F640SPHT-PTL12

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: Page Mode FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 120ns
• Interface: Parallel
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Voltage - Supply: -
• Other names: 425-1857

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
BITS STATUS (BECBLS)
(PBPSS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.3 = V
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS
SR.4 = (PAGE BUFFER) PROGRAM, OTP PROGRAM
SR.5 = BLOCK ERASE AND CLEAR BLOCK LOCK
AND SET BLOCK LOCK BIT STATUS (PBPOPSBLS)
ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Clear Block Lock Bits
0 = Successful Block Erase or Clear Block Lock Bits
1 = Error in (Page Buffer) Program, OTP Program or Set
0 = Successful (Page Buffer) Program, OTP Program or
1 = V
0 = V
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
R
7
Block Lock Bit
Set Block Lock Bit
Locked Block, Operation Abort
PEN
PEN
PEN
STATUS (VPENS)
LOW Detect, Operation Abort
OK
BESS
14
R
6
BECBLS
13
R
5
Table 7. Status Register Definition
PBPOPSBLS
12
R
4
LHF64P01
Check SR.7 or STS to determine block erase, (page buffer)
program, block lock configuration or OTP program
completion. SR.6 - SR.1 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, page
buffer program, block lock configuration, STS configuration
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
after Block Erase, (Page Buffer) Program, Set Block Lock
Bit, Clear Block Lock Bits or OTP Program command
sequences. SR.3 is not guaranteed to report accurate feedback
when V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, (Page Buffer) Program or OTP Program command
sequences. It informs the system, depending on the attempted
operation, if the block lock bit is set. Reading the block lock
configuration codes after writing the Read Identifier Codes/
OTP command indicates block lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
VPENS
11
R
3
PEN
V
PENH
PBPSS
or V
10
R
2
PENLK
NOTES:
.
DPS
R
9
1
PEN
Rev. 0.06
level only
PEN
R
R
8
0
13
level.