LH28F640SPHT-PTL12 Sharp Microelectronics, LH28F640SPHT-PTL12 Datasheet - Page 12

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LH28F640SPHT-PTL12

Manufacturer Part Number
LH28F640SPHT-PTL12
Description
IC FLASH 64MBIT 120NS 56TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F640SPHT-PTL12

Rohs Status
RoHS non-compliant
Format - Memory
FLASH
Memory Type
Page Mode FLASH
Memory Size
64M (8Mx8, 4Mx16)
Speed
120ns
Interface
Parallel
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TSOP
Voltage - Supply
-
Other names
425-1857

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH28F640SPHT-PTL12
Manufacturer:
SHARP
Quantity:
998
NOTES:
1. Bus operations are defined in Table 4.
2. X=Any valid address within the device.
3. The upper byte of the data bus (DQ
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
5. Block erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, write the program sequential address and data of "N" times. Finally, write the any valid
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Block Erase and (Page Buffer)
STS Configuration
Set Block Lock Bit
Clear Block Lock Bits
OTP Program
Program Suspend
Program Resume
IA=Identifier codes address (Refer to Table 3).
QA=Query codes address. Refer to Appendix of LH28F640SP series for details.
BA=Address within the block for block erase, page buffer program or set block lock bit.
WA=Address of memory location for the Program command.
OA=Address of OTP block to be read or programmed (Refer to Figure 3).
ID=Data to be read from identifier codes. (Refer to Table 3).
QD=Data to be read from query database. Refer to Appendix of LH28F640SP series for details.
SRD=Data to be read from status register. Refer to Table 7 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the first edge of CE
N-1=N is the number of the words /bytes to be loaded into a page buffer.
OD=Data within OTP block. Data is latched on the first edge of CE
CC= STS configuration code (Refer to Table 9).
configuration code and the data within OTP block (Refer to Table 3).
The Read Query command is available for reading CFI (Common Flash Interface) information.
or programmed when RP# is V
address within the block to be programmed and the confirm command (D0H).
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
Command
IH
.
Cycles
15
Req’d
Bus
-DQ
1
2
1
2
2
1
1
2
2
2
2
2
2
4
Table 5. Command Definitions
8
) during command writes is ignored in word mode (BYTE#=V
Notes
5,6
5,7
4
4
5
8
8
9
LHF64P01
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(1)
First Bus Cycle
Addr
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
0
, CE
(2)
1
(10)
or CE
Data
40H or
FFH
B0H
D0H
B8H
C0H
E8H
90H
98H
70H
50H
20H
10H
60H
60H
2
(3)
that disables
0
, CE
Oper
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
1
or CE
(1)
Second Bus Cycle
2
IA or OA
that disables
Addr
WA
QA
BA
BA
BA
OA
X
X
X
(2)
IH
: 16 bit).
Rev. 0.06
ID or OD
Data
SRD
D0H
D0H
01H
WD
N-1
QD
OD
CC
10
(3)

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