FDW2507N_Q Fairchild Semiconductor, FDW2507N_Q Datasheet - Page 9

• Manufacturer Part Number: FDW2507N_Q
• Description: MOSFET N-Channel 2.5V Common Drain
• Manufacturer: Fairchild Semiconductor

Specifications of FDW2507N_Q

• Transistor Polarity: N-Channel
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 12 V
• Continuous Drain Current: 7.5 A
• Resistance Drain-source Rds (on): 19 mOhms
• Configuration: Dual Common Quad Drain
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Fall Time: 13 ns
• Forward Transconductance Gfs (max / Min): 31 S
• Minimum Operating Temperature: - 55 C
• Power Dissipation: 1.6 W
• Rise Time: 13 ns
• Typical Turn-off Delay Time: 35 ns

© 2006 Fairchild Semiconductor Corporation
FAN5631/FAN5632 Rev. 1.0.2
Switch Configuration
Shutdown, UVLO, Short-Circuit,
Current-Limit and Thermal Shutdown
The device has an active-low shutdown pin to decrease
supply current to less than 1μA. In shutdown mode, the
supply is disconnected from the output. UVLO triggers
when supply voltage drops below 2V. When the output
voltage is lower than 150mV, a short-circuit protection is
triggered. In this mode, 15 out of 16 pulses during the
switching are skipped and the supply current is limited.
Thermal shutdown triggers at 150ºC.
GND
S4
S3
S1
S2
V
2:1 configuration
Switches in charging phase
Reverse all switches for pumping phase
Figure 15.
IN
V
OUT
C+
C-
2:1 Configuration
C
B
C
OUT
9
Efficiency Optimizer (FAN5632)
In the FAN5632, V
the efficiency optimizer feature. To achieve an
optimized efficiency, the switch mode configuration
transition point is shifted from a 2:1 to a 1:1 mode until
the output voltage falls to 20% of its nominal value. For
example, when the nominal output voltage is 1.5V, the
output voltage is allowed to drop to 1.2V. This maintains
a peak efficiency of 85% for the input voltage range of
2.9V to 3.5V. For normal operation, tie V
GND
1:1 configuration
Switch 3 is always off
Switch 4 is always on
Switches 1 and 2 are in phase 1
Reverse position of switches 1&2 for phase 2
S4
S3
S1
S2
Figure 16.
V
IN
SEL
V OUT
C+
C-
can be tied to ground to enable
1:1 Configuration
C
B
SEL
high.
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C
OUT