C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 63

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F330/1/2/3/4/5
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See
page 125
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator
electrical specifications are given in Table 8.1.
The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini-
tion 8.3). Selecting a longer response time reduces the Comparator supply current. See Table 8.1 for com-
plete timing and power consumption specifications.
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 8.2, settings of 20, 10 or 5 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “8.3. Interrupt Handler” on page 58). The CP0FIF flag is set to
66
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
CP0+
VIN+
VIN-
Disabled
V
OL
Figure 8.2. Comparator Hysteresis Plot
V
OH
+
_
CP0
Positive Hysteresis
Maximum
OUT
Rev. 1.7
Negative Hysteresis
Disabled
Section “14.1. Priority Crossbar Decoder” on
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage