C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 24

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F330/1/2/3/4/5
1.4.
C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The
C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be
configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be config-
ured for push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be
globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See
Figure 1.11.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital sig-
nals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control
registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for the particular application.
1.5.
The C8051F330/1/2/3/4/5 Family includes an SMBus/I
baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
26
Highest
Priority
Lowest
Priority
Programmable Digital I/O and Crossbar
Serial Ports
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
CP0
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 1.11. Digital Crossbar Diagram
2
4
2
2
4
2
8
8
Rev. 1.7
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
2
C interface, a full-duplex UART with enhanced
8
8
PnMDIN Registers
PnMDOUT,
Cells
Cells
I/O
I/O
P0
P1
P0.0
P0.7
P1.0
P1.7