SST25VF032B-80-4I-S2AF Microchip Technology, SST25VF032B-80-4I-S2AF Datasheet - Page 9

• Manufacturer Part Number: SST25VF032B-80-4I-S2AF
• Description: IC FLASH SER 32M 80MHZ SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-80-4I-S2AF

• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Format - Memory: FLASH
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Bus Width: 8 bit
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

32 Mbit SPI Serial Flash
SST25VF032B
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high tran-
sition on CE#. The internal address pointer will automati-
cally increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space. For exam-
High-Speed-Read (80 MHz)
The High-Speed-Read instruction supporting up to 80 MHz
Read is initiated by executing an 8-bit command, 0BH, fol-
lowed by address bits [A
must remain active low for the duration of the High-Speed-
Read cycle. See Figure 6 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
©2009 Silicon Storage Technology, Inc.
SCK
CE#
FIGURE 5: Read Sequence
FIGURE 6: High-Speed-Read Sequence
SO
SI
MODE 3
MODE 0
SCK
CE#
SO
SI
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8
MSB
0 1 2 3 4 5 6 7 8
23
-A
0B
03
0
] and a dummy byte. CE#
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
ADD.
ADD.
15 16
15 16
ADD.
ADD.
23 24
23 24
ADD.
ADD.
9
31 32
ple, once the data from address location 3FFFFFH has
been read, the next output will be from address location
000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
remain active low for the duration of the Read cycle. See
Figure 5 for the Read sequence.
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. For example, once the data
from address location 3FFFFFH has been read, the next
output will be from address location 000000H.
MSB
31 32
D
X
OUT
N
39 40
39 40
D
MSB
OUT
D
N
N+1
OUT
47 48
47 48
D
D
N+1
N+2
OUT
OUT
55 56
55 56
D
D
N+3
N+2
OUT
OUT
63 64
63 64
D
D
N+3
N+4
1327 F06.0
OUT
OUT
S71327-03-000
23
71 72
-A
70
0
]. CE# must
Data Sheet
D
N+4
OUT
1327 F07.1
78
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