SST25VF032B-80-4I-S2AF Microchip Technology, SST25VF032B-80-4I-S2AF Datasheet - Page 15

• Manufacturer Part Number: SST25VF032B-80-4I-S2AF
• Description: IC FLASH SER 32M 80MHZ SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-80-4I-S2AF

• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Format - Memory: FLASH
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Bus Width: 8 bit
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

32 Mbit SPI Serial Flash
SST25VF032B
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. Initiate the Chip-Erase instruction by
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
©2009 Silicon Storage Technology, Inc.
FIGURE 15: Chip-Erase Sequence
FIGURE 16: Read-Status-Register (RDSR) Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
SO
3
SI
05
MODE 3
MODE 0
4
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
15
60 or C7
7
executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. Poll the Busy
bit in the software status register or wait T
tion of the internal self-timed Chip-Erase cycle. See Figure
15 for the Chip-Erase sequence.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 16 for the RDSR instruction sequence.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
1327 F16.0
9
10
Register Out
11
Status
12
13
14
1327 F17.0
S71327-03-000
CE
for the comple-
Data Sheet
05/09