SST25VF032B-80-4I-S2AF Microchip Technology, SST25VF032B-80-4I-S2AF Datasheet - Page 21

• Manufacturer Part Number: SST25VF032B-80-4I-S2AF
• Description: IC FLASH SER 32M 80MHZ SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-80-4I-S2AF

• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Format - Memory: FLASH
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Bus Width: 8 bit
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

32 Mbit SPI Serial Flash
SST25VF032B
TABLE 10: Capacitance
TABLE 11: Reliability Characteristics
TABLE 12: AC Operating Characteristics
©2009 Silicon Storage Technology, Inc.
Parameter
C
C
Symbol
N
T
I
Symbol
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
LTH
DR
CLK
SCKH
SCKL
SCKR
SCKF
CES
CEH
CHS
CHH
CPH
CHZ
CLZ
DS
DH
HLS
HHS
HLH
HHH
HZ
LZ
OH
V
SE
BE
SCE
BP
OUT
IN
END
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
2. Maximum Rise and Fall time may be limited by T
3. Relative to SCK.
4. TBP of AAI-Word Programming is also 10 µs maximum time.
1
1
4
1
1
3
3
3
1
1
3
2
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
Data In Hold Time
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
Description
Output Pin Capacitance
Input Capacitance
Parameter
Endurance
Data Retention
Latch Up
Parameter
(T
A
= 25°C, f = 1 Mhz, other pins open)
SCKH
Min
100
and T
0.1
0.1
18
18
10
10
10
10
10
10
10
10
0
5
5
0
25 MHz
SCKL
Minimum Specification
21
requirements
Max
25
15
20
15
15
25
25
50
10
100 + I
10,000
100
DD
Min
6.5
6.5
0.1
0.1
50
5
5
5
5
0
5
5
5
5
0
2
4
66 MHz
Max
66
25
25
50
10
7
7
7
6
Test Condition
Cycles
Units
Years
mA
V
V
OUT
IN
= 0V
= 0V
Min
0.1
0.1
50
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
6
6
5
5
5
5
0
2
4
5
5
5
5
0
80 MHz
S71327-03-000
Max
80
25
25
50
10
7
7
7
6
Maximum
12 pF
Data Sheet
6 pF
T10.0 1327
T11.0 1327
T12.0 1327
Units
MHz
V/ns
V/ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
05/09