CY7C1460AV25-200BZC Cypress Semiconductor Corp, CY7C1460AV25-200BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1460AV25-200BZC
• Description: IC SRAM 36MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05354 Rev. *D
CY7C1460AV25, BW
CY7C1462AV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Sleep MODE
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQ
Parameter
[1, 2, 3, 4, 5, 6, 7]
Operation
ZZREC
a,b,c,d
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
, CE
after the ZZ input returns LOW.
for CY7C1460AV25 and BW
2
X
, and CE
. See Write Cycle Description table for details.
Description
3
, must remain inactive
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
Address
Used
s
=data when OE is active.
CE
a,b
H
X
L
X
L
X
L
X
X
X
X
L
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
DD
DD
Address
ADV/LD
− 0.2V
Address
Test Conditions
− 0.2V
A1,A0
A1,A0
First
First
00
01
10
11
H
H
H
H
H
X
X
L
L
L
L
L
00
01
10
11
WE
H
X
X
H
X
X
X
X
X
X
L
L
Address
Second
A1,A0
Address
Second
A1,A0
01
10
11
00
BW
X
X
X
X
X
H
H
X
X
X
L
L
01
00
11
10
x
DD
OE CEN CLK
X
X
H
H
X
X
X
X
X
X
L
L
)
2t
Address
Min.
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
s
A1,A0
Third
CYC
Address
0
and DQP
A1,A0
10
11
00
01
H
X
L
L
L
L
L
L
L
L
L
L
Third
10
00
01
11
L-H
L-H
L-H Data Out (Q)
L-H Data Out (Q)
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
X
2t
2t
Max.
= Three-state when
100
CYC
CYC
Page 8 of 27
Address
Data In (D)
Data In (D)
Address
Fourth
Fourth
A1,A0
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
A1,A0
00
01
10
11
11
10
01
00
DQ
–
Unit
mA
ns
ns
ns
ns
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