CY7C1460AV25-200BZC Cypress Semiconductor Corp, CY7C1460AV25-200BZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1460AV25-200BZC
• Description: IC SRAM 36MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05354 Rev. *D
Pin Configurations
Pin Definitions
Pin Name
ADV/LD
BW
BW
BW
BW
BW
BW
BW
CLK
BW
WE
A0
A1
A
a
b
d
e
g
h
c
f
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Synchronous
Synchronous
Synchronous
Synchronous
I/O Type
Input-
Input-
Input-
Input-
Input-
Clock
DQPg
DQg
DQg
DQg
DQg
DQPd
DQc
NC
DQh
DQh
DQh
DQc
DQc
DQh
DQd
DQd
DQd
DQd
DQc
1
(continued)
DQg
DQg
DQg
DQg
DQPc
DQc
NC
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQc
DQh
DQd
DQc
DQc
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQ
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
2
c
controls DQ
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
NC/144M
V
TMS
V
CLK
V
V
V
BWS
V
V
V
V
V
BWS
V
V
A
SS
DDQ
DDQ
DDQ
SS
SS
DDQ
SS
DDQ
SS
A
DDQ
SS
3
f
c
h
and DQP
CY7C1464AV25 (512K x 72)
BWS
V
V
BWS
V
V
V
V
V
V
NC
NC
V
V
CE
NC
TDI
c
A
A
DDQ
DDQ
SS
SS
DDQ
DDQ
SS
DDQ
SS
DDQ
4
and DQP
2
g
d
f,
BW
NC/576M
NC/72M
NC/1G
V
V
V
V
V
V
V
V
NC
V
V
A
V
A
DD
A
NC
SS
DD
SS
SS
5
DD
DD
SS
g
DD
DD
SS
c
, BW
controls DQ
ADV/LD
d
NC
CEN
MODE
NC
NC
CE
OE
NC
NC
WE
NC
NC
V
V
ZZ
controls DQ
A1
A0
A
DD
DD
6
1
a
Pin Description
controls DQ
g
and DQP
NC
V
V
V
V
V
V
A
V
V
V
V
V
NC
A
A
NC
A
A
DD
SS
7
DD
DD
DD
SS
DD
SS
DD
SS
SS
d
and DQP
g,
V
V
BWS
V
V
V
V
BWS
V
V
a
V
V
TDO
CE
NC
NC
NC
SS
DDQ
A
BW
DDQ
SS
A
SS
DDQ
DDQ
DDQ
SS
DDQ
and DQP
8
3
b
e
h
d
, BW
controls DQ
NC/288M
BWS
V
V
V
V
V
V
V
V
BWS
V
V
V
V
TCK
NC
SS
A
SS
DDQ
DDQ
SS
DDQ
SS
SS
DDQ
SS
A
DDQ
DDQ
a
9
e
, BW
controls DQ
f
a
b
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
DQb
DQb
DQPf
DQb
DQb
DQPa
controls DQ
h
DQf
NC
DQa
DQa
DQa
DQf
DQf
DQa
DQe
DQe
DQe
DQe
DQf
and DQP
10
e
and DQP
DQb
DQb
DQb
DQb
DQPb
DQf
NC
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQf
DQa
DQe
DQf
DQf
11
h
b
Page 5 of 27
.
and DQP
e,
BW
b
f
,
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