CY7C1460AV25-200BZC Cypress Semiconductor Corp, CY7C1460AV25-200BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1460AV25-200BZC
• Description: IC SRAM 36MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05354 Rev. *D
Pin Definitions
Pin Name
NC /144M
NC /288M
NC /576M
NC/72M
NC /1G
MODE
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
V
CEN
TDO
TMS
DQ
DQ
DQ
DQ
DQ
DQ
TCK
CE
CE
CE
DQ
V
DQ
V
TDI
OE
NC
ZZ
DDQ
DD
SS
1
2
3
a
b
d
e
g
h
c
f
a
b
c
d
e
g
h
f
JTAG serial output
Test Mode Select
I/O Power Supply Power supply for the I/O circuitry.
JTAG serial input
Input Strap Pin
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG-Clock
I/O Type
Ground
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O-
N/A
N/A
N/A
N/A
N/A
N/A
(continued)
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
cally tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
BW
DQP
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
2
1
1
c
and CE
, and DQP
and CE
and CE
g
is controlled by BW
2
3
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
X
d
during the previous clock rise of the read cycle. The direction of the pins is
is controlled by BW
a
is controlled by BW
g
, DQP
a
–DQ
h
d
is controlled by BW
are placed in a tri-state condition. The outputs are automati-
d
, DQP
Pin Description
a
e
, DQP
is controlled by BW
b
is controlled by BW
h
.
e
, DQP
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
b
f
, DQP
is controlled by BW
c
is controlled by
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