CY7C1460AV25-200BZC Cypress Semiconductor Corp, CY7C1460AV25-200BZC Datasheet - Page 12

• Manufacturer Part Number: CY7C1460AV25-200BZC
• Description: IC SRAM 36MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05354 Rev. *D
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
TAP Timing
TAP AC Switching Characteristics
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes:
10. Test conditions are specified using the load in TAP AC test Conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
9. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
Over the Operating Range
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
F
t
TL
= 1 ns.
3
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
[9, 10]
UNDEFINED
4
t TDOX
t TDOV
5
Min.
50
20
20
0
5
5
5
5
5
5
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
6
Max.
20
10
Page 12 of 27
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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