S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 80

• Manufacturer Part Number: S9S08SG8E2VTJR
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTJR

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 5 Resets, Interrupts, and General System Control
5.7.7
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU. This register should be written during the user’s reset initialization program to set
the desired controls even if the desired settings are the same as the reset settings
74
1
2
Any other Reset:
Power-on Reset:
PPDACK
This bit can be written only one time after power-on reset. Additional writes are ignored.
This bit can be written only one time after reset. Additional writes are ignored.
PPDC
LVWV
PPDF
Field
LVDV
LVD Reset:
5
4
3
2
0
System Power Management Status and Control 2 Register
(SPMSC2)
Low-Voltage Detect Voltage Select — This write-once bit selects the low voltage detect (LVD) trip point setting.
It also selects the warning voltage range. See
Low-Voltage Warning Voltage Select — This bit selects the low voltage warning (LVW) trip point voltage. See
Table
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit
Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
W
R
5-11.
0
7
0
0
0
= Unimplemented or Reserved
Table 5-10. SPMSC2 Register Field Descriptions
0
0
0
0
6
MC9S08SG32 Data Sheet, Rev. 8
LVDV
0
u
u
5
1
LVWV
Table
u
4
0
u
Description
5-11.
PPDF
0
0
0
3
PPDACK
u = Unaffected by reset
0
0
0
0
2
es
Freescale Semiconductor
0
0
0
0
1
PPDC
0
0
0
0
2