S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 223

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S9S08SG8E2VTJR

Manufacturer Part Number
S9S08SG8E2VTJR
Description
8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S08SG8E2VTJR

Rohs
yes
Core
HCS08
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
8 KB
Data Ram Size
512 B
On-chip Adc
Yes
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
12
Interface Type
I2C, SCI, SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
2.7 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2VTJR
Manufacturer:
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Quantity:
20 000
1
14.2.7
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
14.3
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
14.3.1
As shown in
Freescale Semiconductor
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
Reset
TXINV
Field
ORIE
NEIE
FEIE
PEIE
4
3
2
1
0
W
R
1
Functional Description
SCI Data Register (SCID)
Baud Rate Generation
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
R7
T7
Figure
0
7
14-12, the clock source for the SCI baud rate generator is the bus-rate clock.
R6
T6
0
6
Table 14-7. SCIC3 Field Descriptions (continued)
Figure 14-11. SCI Data Register (SCID)
R5
T5
0
5
MC9S08SG32 Data Sheet, Rev. 8
R4
T4
0
4
Description
Chapter 14 Serial Communications Interface (S08SCIV4)
R3
T3
3
0
R2
T2
0
2
R1
T1
0
1
R0
T0
0
0
217

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