S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 162

• Manufacturer Part Number: S9S08SG8E2VTJR
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTJR

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 10 Inter-Integrated Circuit (S08IICV2)
For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100kbps.
156
MULT
Field
ICR
7–6
5–0
IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider,
generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time.
Table 10-5
The SCL divider multiplied by multiplier factor mul generates IIC baud rate.
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
MULT
0x2
0x1
0x1
0x0
0x0
provides the SCL divider and hold values for corresponding values of the ICR.
SCL Start hold time = bus period (s)
SCL Stop hold time = bus period (s)
Table 10-4. Hold Time Values for 8 MHz Bus Speed
SDA hold time = bus period (s)
Table 10-3. IICF Field Descriptions
0x0B
0x00
0x07
0x14
0x18
ICR
MC9S08SG32 Data Sheet, Rev. 8
IIC baud rate
3.500
2.500
2.250
2.125
1.125
SDA
=
Description
-------------------------------------------- -
mul SCLdivider
bus speed (Hz)
×
×
×
×
mul
mul
mul
Hold Times (μs)
×
×
×
SCL Start
SDA hold value
SCL Start hold value
SCL Stop hold value
3.000
4.000
4.000
4.250
4.750
SCL Stop
5.500
5.250
5.250
5.125
5.125
Freescale Semiconductor
Eqn. 10-1
Eqn. 10-2
Eqn. 10-3
Eqn. 10-4