W25Q16BVSSIG Winbond Electronics, W25Q16BVSSIG Datasheet
W25Q16BVSSIG
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W25Q16BVSSIG Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: July 08, 2010 - 1 - W25Q16BV Revision F ...
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... Block Protect Bits (BP2, BP1, BP0)....................................................................................13 11.1.4 Top/Bottom Block Protect (TB)...........................................................................................13 11.1.5 Sector/Block Protect (SEC) ................................................................................................13 11.1.6 Status Register Protect (SRP1, SRP0)...............................................................................14 11.1.7 Erase Suspend Status (SUS) .............................................................................................14 11.1.8 Quad Enable (QE) ..............................................................................................................14 11.1.9 Status Register Memory Protection ....................................................................................16 11.2 INSTRUCTIONS................................................................................................................. 17 11.2.1 Manufacturer and Device Identification ..............................................................................17 Table of Contents - 2 - W25Q16BV ...
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Instruction Set Table 1 (Erase, Program Instructions) ........................................................18 11.2.3 Instruction Set Table 2 (Read Instructions) ........................................................................19 11.2.4 Instruction Set Table 3 (ID, Security Instructions)...............................................................20 11.2.5 Write Enable (06h)..............................................................................................................21 11.2.6 Write Disable (04h).............................................................................................................21 11.2.7 Read Status Register-1 (05h) and Read ...
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Serial Output Timing........................................................................................................... 59 12.9 Serial Input Timing.............................................................................................................. 59 12.10 Hold Timing ....................................................................................................................... 59 13. PACKAGE SPECIFICATION.......................................................................................................... 60 13.1 8-Pin SOIC 150-mil (Package Code SN) ........................................................................... 60 13.2 8-Pin SOIC 208-mil (Package Code SS) ........................................................................... 61 13.3 8-Pin PDIP ...
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... Dual Output and 416MHz for Quad Output when using the Fast Read Dual/Quad Output instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation ...
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PIN CONFIGURATION SOIC 150 / 208-MIL /CS /CS DO ( /WP (IO /WP ( GND GND Figure 1a. W25Q16BV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN ...
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PAD CONFIGURATION PDIP 300-MIL /CS /CS DO ( /WP (IO /WP ( GND GND Figure 1c. W25Q16BV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 150/208-MIL, PDIP 300-MIL AND WSON ...
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PIN CONFIGURATION SOIC 300-MIL /HOLD (IO /HOLD ( VCC VCC N/C N/C N/C N/C N/C N/C N/C N/C /CS / Figure 1d. W25Q16BV Pin Assignments, 16-pin SOIC 300-mil (Package ...
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... Status Register’s Block Protect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2 ...
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... CLK SPI SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q16BV Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh xx2FFFh xx2FFFh • ...
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FUNCTIONAL DESCRIPTION 10.1 SPI OPERATIONS 10.1.1 Standard SPI Instructions The W25Q16BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...
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... Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits ...
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Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply ...
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SRP0 SRP0 STATUS REGISTER PROTECT 0 STATUS REGISTER PROTECT 0 (non-volatile) (non-volatile) SECTOR PROTECT SECTOR PROTECT (non-volatile) (non-volatile) TOP/BOTTOM PROTECT TOP/BOTTOM PROTECT (non-volatile) (non-volatile) BLOCK PROTECT BITS BLOCK PROTECT BITS (non-volatile) (non-volatile) WRITE ENABLE LATCH WRITE ENABLE LATCH ERASE/WRITE IN ...
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... Status Register Memory Protection (1) STATUS REGISTER SEC TB BP2 BP1 BP0 Note don’t care W25Q16BV (16M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 31 1F0000h – 1FFFFFh 30 and 31 1E0000h – 1FFFFFh 28 thru 31 1C0000h – 1FFFFFh 24 thru 31 180000h – 1FFFFFh 16 thru 31 100000h – 1FFFFFh 0 000000h – ...
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... Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 INSTRUCTION NAME (CODE) Write Enable 06h Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program 02h Quad Page Program 32h Sector Erase ...
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Instruction Set Table 2 (Read Instructions) BYTE 1 INSTRUCTION NAME (CODE) Read Data 03h Fast Read 0Bh Fast Read Dual Output 3Bh Fast Read Dual I/O BBh Fast Read Quad Output 6Bh Fast Read Quad I/O EBh (7) Word ...
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... See Manufacturer and Device Identification table for Device ID information. BYTE 2 BYTE 3 dummy dummy dummy dummy A23-A8 A7-A0, M[7:0] A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy - 20 - W25Q16BV BYTE 4 BYTE 5 (1) dummy (ID7-ID0) 00h (MF7-MF0) (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip ...
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Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 ...
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... The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table and description). The Write Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1 set ...
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... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F (see AC Electrical Characteristics). This is accomplished by adding eight R “dummy” clocks ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO twice the rate of standard SPI devices. The Fast ...
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Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO executed before the device will accept the Fast ...
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Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...
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Figure 12b. Fast Read Dual I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV Publication Release Date: July 08, 2010 Revision F ...
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Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO clocks are required ...
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Figure 13b. Fast Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV Publication Release Date: July 08, 2010 Revision F ...
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Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required ...
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Figure 14b. Word Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV ...
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Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As ...
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Figure 15b. Octal Word Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV ...
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... Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Erase Suspend (75h) The Erase Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation and then read from or program data to, any other sectors or blocks. The Erase Suspend instruction sequence is shown ...
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Erase Resume (7Ah) The Erase Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation after an Erase Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To ...
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Figure 25b. Release Power-down / Device ID Instruction Sequence Diagram - 46 - W25Q16BV ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q16BV device. The ID number can be used in conjunction with user software methods to help prevent ...
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... The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 30. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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Continuous Read Mode Reset (FFh or FFFFh) For Fast Read Dual/Quad I/O operations, “Continuous Read Mode” Bits (M7-0) are implemented to further reduce instruction overhead. By setting the (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O operation ...
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ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) VSL t (1) PUW V (1) WI ...
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DC Electrical Characteristics PARAMETER SYMBOL IN (1) Input Capacitance C (1) Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 3.0V-3.6V VCC ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Setup Time relative to CLK /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z ...
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Serial Output Timing 12.9 Serial Input Timing 12.10 Hold Timing Publication Release Date: July 08, 2010 - 59 - W25Q16BV Revision F ...
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PACKAGE SPECIFICATION 13.1 8-Pin SOIC 150-mil (Package Code SN SEATING PLANE SEATING PLANE SYMBOL (3) E ( (4) ...
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SOIC 208-mil (Package Code SS) SYMBOL Min A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5.18 E1 5.13 ( 7.70 L 0.50 y --- θ 0° Notes: 1. Controlling ...
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PDIP 300-mil (Package Code DA) SYMBO L Min A --- A1 0.38 A2 3. 6.22 L 2.92 e 8.51 B θ 0° ° MILLIMETERS Nom Max Min --- 5.33 --- --- --- 0.015 3.30 ...
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WSON (Package Code ZP) SYMBOL Min A 0.70 A1 0.00 b 0.35 C --- D 5.90 D2 3.35 4. 4.25 ( 0.55 y 0.00 MILLIMETERS Nom Max Min 0.75 0.80 0.028 0.02 0.05 ...
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WSON Cont’d. SYMBOL Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not ...
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SOIC 300-mil (Package Code SF) SYMBOL Min A 2.36 A1 0.10 A2 --- b 0.33 C 0.18 D 10.08 E 10.01 E1 7.39 ( 0.38 y --- θ 0° Notes: 1. Controlling dimensions: inches, unless otherwise ...
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... ORDERING INFORMATION W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 16B = 16M-bit V = 2. 8-pin SOIC 150-mil SS = 8-pin SOIC 208-mil I = Industrial (-40°C to +85°C) ( Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Green Package with Status Register Power Lock-Down & OTP enabled ...
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... PDIP-8 300mil Note: 1. WSON package type ZP is not used in the top side marking. 2. These Package types are Special Order Only, please contact Winbond for more information. PRODUCT NUMBER TOP SIDE MARKING W25Q16BVSNIG W25Q16BVSNIP W25Q16BVSSIG W25Q16BVSSIP W25Q16BVSFIG W25Q16BVSFIP W25Q16BVZPIG W25Q16BVZPIP W25Q16BVDAIG W25Q16BVDAIP ...
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... F 07/08/10 Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life ...